sci.tan.qmsg

VHDL写的SCI接口。quartusII6.0的工程！

{ "Info" "ITDB_FULL_TPD_RESULT" "rd data\[2\] 10.771 ns Longest " "Info: Longest tpd from source pin \"rd\" to destination pin \"data\[2\]\" is 10.771 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rd 1 PIN PIN_14 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_14; Fanout = 1; PIN Node = 'rd'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "" { rd } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.062 ns) + CELL(0.442 ns) 6.973 ns process0~0 2 COMB LC_X1_Y23_N0 10 " "Info: 2: + IC(5.062 ns) + CELL(0.442 ns) = 6.973 ns; Loc. = LC_X1_Y23_N0; Fanout = 10; COMB Node = 'process0~0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "5.504 ns" { rd process0~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.724 ns) + CELL(2.074 ns) 10.771 ns data\[2\] 3 PIN PIN_6 0 " "Info: 3: + IC(1.724 ns) + CELL(2.074 ns) = 10.771 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'data\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "3.798 ns" { process0~0 data[2] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.985 ns ( 37.00 % ) " "Info: Total cell delay = 3.985 ns ( 37.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.786 ns ( 63.00 % ) " "Info: Total interconnect delay = 6.786 ns ( 63.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "10.771 ns" { rd process0~0 data[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.771 ns" { rd rd~out0 process0~0 data[2] } { 0.000ns 0.000ns 5.062ns 1.724ns } { 0.000ns 1.469ns 0.442ns 2.074ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "din_latch\[6\] data\[6\] wr 5.092 ns register " "Info: th for register \"din_latch\[6\]\" (data pin = \"data\[6\]\", clock pin = \"wr\") is 5.092 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wr destination 11.251 ns + Longest register " "Info: + Longest clock path from clock \"wr\" to destination register is 11.251 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns wr 1 CLK PIN_20 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_20; Fanout = 10; CLK Node = 'wr'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "" { wr } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(9.071 ns) + CELL(0.711 ns) 11.251 ns din_latch\[6\] 2 REG LC_X1_Y23_N9 1 " "Info: 2: + IC(9.071 ns) + CELL(0.711 ns) = 11.251 ns; Loc. = LC_X1_Y23_N9; Fanout = 1; REG Node = 'din_latch\[6\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "9.782 ns" { wr din_latch[6] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 19.38 % ) " "Info: Total cell delay = 2.180 ns ( 19.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.071 ns ( 80.62 % ) " "Info: Total interconnect delay = 9.071 ns ( 80.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "11.251 ns" { wr din_latch[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.251 ns" { wr wr~out0 din_latch[6] } { 0.000ns 0.000ns 9.071ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 50 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.174 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data\[6\] 1 PIN PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_12; Fanout = 1; PIN Node = 'data\[6\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "" { data[6] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns data\[6\]~1 2 COMB IOC_X0_Y23_N1 1 " "Info: 2: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = IOC_X0_Y23_N1; Fanout = 1; COMB Node = 'data\[6\]~1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "1.469 ns" { data[6] data[6]~1 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.590 ns) + CELL(0.115 ns) 6.174 ns din_latch\[6\] 3 REG LC_X1_Y23_N9 1 " "Info: 3: + IC(4.590 ns) + CELL(0.115 ns) = 6.174 ns; Loc. = LC_X1_Y23_N9; Fanout = 1; REG Node = 'din_latch\[6\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "4.705 ns" { data[6]~1 din_latch[6] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 25.66 % ) " "Info: Total cell delay = 1.584 ns ( 25.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.590 ns ( 74.34 % ) " "Info: Total interconnect delay = 4.590 ns ( 74.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "6.174 ns" { data[6] data[6]~1 din_latch[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.174 ns" { data[6] data[6]~1 din_latch[6] } { 0.000ns 0.000ns 4.590ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "11.251 ns" { wr din_latch[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.251 ns" { wr wr~out0 din_latch[6] } { 0.000ns 0.000ns 9.071ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "6.174 ns" { data[6] data[6]~1 din_latch[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.174 ns" { data[6] data[6]~1 din_latch[6] } { 0.000ns 0.000ns 4.590ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 28 12:14:09 2006 " "Info: Processing ended: Wed Jun 28 12:14:09 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}