sci.tan.qmsg

VHDL写的SCI接口。quartusII6.0的工程！

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register rxdF register do_latch\[2\] 239.29 MHz 4.179 ns Internal " "Info: Clock \"clk\" has Internal fmax of 239.29 MHz between source register \"rxdF\" and destination register \"do_latch\[2\]\" (period= 4.179 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.918 ns + Longest register register " "Info: + Longest register to register delay is 3.918 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rxdF 1 REG LC_X1_Y23_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y23_N7; Fanout = 3; REG Node = 'rxdF'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "" { rxdF } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.590 ns) 1.857 ns do_latch\[0\]~7 2 COMB LC_X2_Y24_N7 8 " "Info: 2: + IC(1.267 ns) + CELL(0.590 ns) = 1.857 ns; Loc. = LC_X2_Y24_N7; Fanout = 8; COMB Node = 'do_latch\[0\]~7'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "1.857 ns" { rxdF do_latch[0]~7 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.194 ns) + CELL(0.867 ns) 3.918 ns do_latch\[2\] 3 REG LC_X1_Y25_N6 1 " "Info: 3: + IC(1.194 ns) + CELL(0.867 ns) = 3.918 ns; Loc. = LC_X1_Y25_N6; Fanout = 1; REG Node = 'do_latch\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "2.061 ns" { do_latch[0]~7 do_latch[2] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.457 ns ( 37.19 % ) " "Info: Total cell delay = 1.457 ns ( 37.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.461 ns ( 62.81 % ) " "Info: Total interconnect delay = 2.461 ns ( 62.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "3.918 ns" { rxdF do_latch[0]~7 do_latch[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.918 ns" { rxdF do_latch[0]~7 do_latch[2] } { 0.000ns 1.267ns 1.194ns } { 0.000ns 0.590ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.245 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 31 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 31; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "" { clk } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.711 ns) 3.245 ns do_latch\[2\] 2 REG LC_X1_Y25_N6 1 " "Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X1_Y25_N6; Fanout = 1; REG Node = 'do_latch\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "1.776 ns" { clk do_latch[2] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.18 % ) " "Info: Total cell delay = 2.180 ns ( 67.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 32.82 % ) " "Info: Total interconnect delay = 1.065 ns ( 32.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "3.245 ns" { clk do_latch[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 do_latch[2] } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.245 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 31 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 31; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "" { clk } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.711 ns) 3.245 ns rxdF 2 REG LC_X1_Y23_N7 3 " "Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X1_Y23_N7; Fanout = 3; REG Node = 'rxdF'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "1.776 ns" { clk rxdF } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.18 % ) " "Info: Total cell delay = 2.180 ns ( 67.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 32.82 % ) " "Info: Total interconnect delay = 1.065 ns ( 32.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "3.245 ns" { clk rxdF } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 rxdF } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "3.245 ns" { clk do_latch[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 do_latch[2] } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "3.245 ns" { clk rxdF } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 rxdF } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 37 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "3.918 ns" { rxdF do_latch[0]~7 do_latch[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.918 ns" { rxdF do_latch[0]~7 do_latch[2] } { 0.000ns 1.267ns 1.194ns } { 0.000ns 0.590ns 0.867ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "3.245 ns" { clk do_latch[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 do_latch[2] } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "3.245 ns" { clk rxdF } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 rxdF } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "wr " "Info: No valid register-to-register data paths exist for clock \"wr\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "do_latch\[4\] rd clk 7.468 ns register " "Info: tsu for register \"do_latch\[4\]\" (data pin = \"rd\", clock pin = \"clk\") is 7.468 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.676 ns + Longest pin register " "Info: + Longest pin to register delay is 10.676 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rd 1 PIN PIN_14 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_14; Fanout = 1; PIN Node = 'rd'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "" { rd } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.062 ns) + CELL(0.442 ns) 6.973 ns process0~0 2 COMB LC_X1_Y23_N0 10 " "Info: 2: + IC(5.062 ns) + CELL(0.442 ns) = 6.973 ns; Loc. = LC_X1_Y23_N0; Fanout = 10; COMB Node = 'process0~0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "5.504 ns" { rd process0~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(0.442 ns) 8.615 ns do_latch\[0\]~7 3 COMB LC_X2_Y24_N7 8 " "Info: 3: + IC(1.200 ns) + CELL(0.442 ns) = 8.615 ns; Loc. = LC_X2_Y24_N7; Fanout = 8; COMB Node = 'do_latch\[0\]~7'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "1.642 ns" { process0~0 do_latch[0]~7 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.194 ns) + CELL(0.867 ns) 10.676 ns do_latch\[4\] 4 REG LC_X1_Y25_N2 1 " "Info: 4: + IC(1.194 ns) + CELL(0.867 ns) = 10.676 ns; Loc. = LC_X1_Y25_N2; Fanout = 1; REG Node = 'do_latch\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "2.061 ns" { do_latch[0]~7 do_latch[4] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.220 ns ( 30.16 % ) " "Info: Total cell delay = 3.220 ns ( 30.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.456 ns ( 69.84 % ) " "Info: Total interconnect delay = 7.456 ns ( 69.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "10.676 ns" { rd process0~0 do_latch[0]~7 do_latch[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.676 ns" { rd rd~out0 process0~0 do_latch[0]~7 do_latch[4] } { 0.000ns 0.000ns 5.062ns 1.200ns 1.194ns } { 0.000ns 1.469ns 0.442ns 0.442ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 37 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.245 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 31 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 31; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "" { clk } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.711 ns) 3.245 ns do_latch\[4\] 2 REG LC_X1_Y25_N2 1 " "Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X1_Y25_N2; Fanout = 1; REG Node = 'do_latch\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "1.776 ns" { clk do_latch[4] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.18 % ) " "Info: Total cell delay = 2.180 ns ( 67.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 32.82 % ) " "Info: Total interconnect delay = 1.065 ns ( 32.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "3.245 ns" { clk do_latch[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 do_latch[4] } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "10.676 ns" { rd process0~0 do_latch[0]~7 do_latch[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.676 ns" { rd rd~out0 process0~0 do_latch[0]~7 do_latch[4] } { 0.000ns 0.000ns 5.062ns 1.200ns 1.194ns } { 0.000ns 1.469ns 0.442ns 0.442ns 0.867ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "3.245 ns" { clk do_latch[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 do_latch[4] } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "wr txd din_latch\[4\] 19.337 ns register " "Info: tco from clock \"wr\" to destination pin \"txd\" through register \"din_latch\[4\]\" is 19.337 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wr source 11.251 ns + Longest register " "Info: + Longest clock path from clock \"wr\" to source register is 11.251 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns wr 1 CLK PIN_20 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_20; Fanout = 10; CLK Node = 'wr'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "" { wr } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(9.071 ns) + CELL(0.711 ns) 11.251 ns din_latch\[4\] 2 REG LC_X1_Y23_N2 1 " "Info: 2: + IC(9.071 ns) + CELL(0.711 ns) = 11.251 ns; Loc. = LC_X1_Y23_N2; Fanout = 1; REG Node = 'din_latch\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "9.782 ns" { wr din_latch[4] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 19.38 % ) " "Info: Total cell delay = 2.180 ns ( 19.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.071 ns ( 80.62 % ) " "Info: Total interconnect delay = 9.071 ns ( 80.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "11.251 ns" { wr din_latch[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.251 ns" { wr wr~out0 din_latch[4] } { 0.000ns 0.000ns 9.071ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 50 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.862 ns + Longest register pin " "Info: + Longest register to pin delay is 7.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns din_latch\[4\] 1 REG LC_X1_Y23_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y23_N2; Fanout = 1; REG Node = 'din_latch\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "" { din_latch[4] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.540 ns) + CELL(0.590 ns) 1.130 ns Mux~160 2 COMB LC_X1_Y23_N9 1 " "Info: 2: + IC(0.540 ns) + CELL(0.590 ns) = 1.130 ns; Loc. = LC_X1_Y23_N9; Fanout = 1; COMB Node = 'Mux~160'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "1.130 ns" { din_latch[4] Mux~160 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.590 ns) 2.160 ns Mux~161 3 COMB LC_X1_Y23_N8 1 " "Info: 3: + IC(0.440 ns) + CELL(0.590 ns) = 2.160 ns; Loc. = LC_X1_Y23_N8; Fanout = 1; COMB Node = 'Mux~161'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "1.030 ns" { Mux~160 Mux~161 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.192 ns) + CELL(0.442 ns) 3.794 ns Mux~164 4 COMB LC_X1_Y21_N4 1 " "Info: 4: + IC(1.192 ns) + CELL(0.442 ns) = 3.794 ns; Loc. = LC_X1_Y21_N4; Fanout = 1; COMB Node = 'Mux~164'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "1.634 ns" { Mux~161 Mux~164 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.407 ns) + CELL(0.442 ns) 4.643 ns Mux~165 5 COMB LC_X1_Y21_N2 1 " "Info: 5: + IC(0.407 ns) + CELL(0.442 ns) = 4.643 ns; Loc. = LC_X1_Y21_N2; Fanout = 1; COMB Node = 'Mux~165'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "0.849 ns" { Mux~164 Mux~165 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.095 ns) + CELL(2.124 ns) 7.862 ns txd 6 PIN PIN_19 0 " "Info: 6: + IC(1.095 ns) + CELL(2.124 ns) = 7.862 ns; Loc. = PIN_19; Fanout = 0; PIN Node = 'txd'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "3.219 ns" { Mux~165 txd } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.188 ns ( 53.27 % ) " "Info: Total cell delay = 4.188 ns ( 53.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.674 ns ( 46.73 % ) " "Info: Total interconnect delay = 3.674 ns ( 46.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "7.862 ns" { din_latch[4] Mux~160 Mux~161 Mux~164 Mux~165 txd } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.862 ns" { din_latch[4] Mux~160 Mux~161 Mux~164 Mux~165 txd } { 0.000ns 0.540ns 0.440ns 1.192ns 0.407ns 1.095ns } { 0.000ns 0.590ns 0.590ns 0.442ns 0.442ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "11.251 ns" { wr din_latch[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.251 ns" { wr wr~out0 din_latch[4] } { 0.000ns 0.000ns 9.071ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "7.862 ns" { din_latch[4] Mux~160 Mux~161 Mux~164 Mux~165 txd } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.862 ns" { din_latch[4] Mux~160 Mux~161 Mux~164 Mux~165 txd } { 0.000ns 0.540ns 0.440ns 1.192ns 0.407ns 1.095ns } { 0.000ns 0.590ns 0.590ns 0.442ns 0.442ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}