sci.fit.eqn

VHDL写的SCI接口。quartusII6.0的工程！

--operation mode is normal

A1L55 = !rd & (!cs);


--scit_v[0] is scit_v[0] at LC_X1_Y22_N1
--operation mode is arithmetic

scit_v[0]_lut_out = !scit_v[0];
scit_v[0] = DFFEAS(scit_v[0]_lut_out, GLOBAL(clk), GLOBAL(reset), , , ~GND, , , A1L54);

--A1L91 is scit_v[0]~127 at LC_X1_Y22_N1
--operation mode is arithmetic

A1L91_cout_0 = scit_v[0];
A1L91 = CARRY(A1L91_cout_0);

--A1L92 is scit_v[0]~127COUT1_131 at LC_X1_Y22_N1
--operation mode is arithmetic

A1L92_cout_1 = scit_v[0];
A1L92 = CARRY(A1L92_cout_1);


--A1L58 is process3~2 at LC_X1_Y22_N9
--operation mode is normal

A1L58 = scit_v[0] & A1L59 & scit_v[1] & scit_v[5];


--A1L57 is process3~0 at LC_X2_Y23_N4
--operation mode is normal

A1L57 = !cs & (!wr);


--A1L88 is scir_v~166 at LC_X3_Y24_N9
--operation mode is normal

A1L88 = !scir_v[5] & (!scir_v[4] # !scir_v[3] # !scir_v[2]);


--do_latch[0] is do_latch[0] at LC_X2_Y24_N8
--operation mode is normal

do_latch[0]_lut_out = d_fb[0];
do_latch[0] = DFFEAS(do_latch[0]_lut_out, GLOBAL(clk), VCC, , A1L40, , , , );


--do_latch[1] is do_latch[1] at LC_X1_Y24_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

do_latch[1]_lut_out = GND;
do_latch[1] = DFFEAS(do_latch[1]_lut_out, GLOBAL(clk), VCC, , A1L40, d_fb[1], , , VCC);


--do_latch[2] is do_latch[2] at LC_X1_Y25_N6
--operation mode is normal

do_latch[2]_lut_out = d_fb[2];
do_latch[2] = DFFEAS(do_latch[2]_lut_out, GLOBAL(clk), VCC, , A1L40, , , , );


--do_latch[3] is do_latch[3] at LC_X1_Y25_N9
--operation mode is normal

do_latch[3]_lut_out = d_fb[3];
do_latch[3] = DFFEAS(do_latch[3]_lut_out, GLOBAL(clk), VCC, , A1L40, , , , );


--do_latch[4] is do_latch[4] at LC_X1_Y25_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

do_latch[4]_lut_out = GND;
do_latch[4] = DFFEAS(do_latch[4]_lut_out, GLOBAL(clk), VCC, , A1L40, d_fb[4], , , VCC);


--do_latch[5] is do_latch[5] at LC_X1_Y25_N5
--operation mode is normal

do_latch[5]_lut_out = d_fb[5];
do_latch[5] = DFFEAS(do_latch[5]_lut_out, GLOBAL(clk), VCC, , A1L40, , , , );


--do_latch[6] is do_latch[6] at LC_X1_Y25_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

do_latch[6]_lut_out = GND;
do_latch[6] = DFFEAS(do_latch[6]_lut_out, GLOBAL(clk), VCC, , A1L40, d_fb[6], , , VCC);


--do_latch[7] is do_latch[7] at LC_X1_Y25_N8
--operation mode is normal

do_latch[7]_lut_out = d_fb[7];
do_latch[7] = DFFEAS(do_latch[7]_lut_out, GLOBAL(clk), VCC, , A1L40, , , , );


--d_fb[0] is d_fb[0] at LC_X1_Y24_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

d_fb[0]_lut_out = GND;
d_fb[0] = DFFEAS(d_fb[0]_lut_out, GLOBAL(clk), GLOBAL(reset), , A1L61, d_fb[1], , , VCC);


--A1L40 is do_latch[0]~7 at LC_X2_Y24_N7
--operation mode is normal

A1L40 = rxdF & !A1L55 & A1L87 & A1L56;


--d_fb[1] is d_fb[1] at LC_X1_Y24_N7
--operation mode is normal

d_fb[1]_lut_out = d_fb[2];
d_fb[1] = DFFEAS(d_fb[1]_lut_out, GLOBAL(clk), GLOBAL(reset), , A1L61, , , , );


--d_fb[2] is d_fb[2] at LC_X1_Y24_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

d_fb[2]_lut_out = GND;
d_fb[2] = DFFEAS(d_fb[2]_lut_out, GLOBAL(clk), GLOBAL(reset), , A1L61, d_fb[3], , , VCC);


--d_fb[3] is d_fb[3] at LC_X1_Y24_N9
--operation mode is normal

d_fb[3]_lut_out = d_fb[4];
d_fb[3] = DFFEAS(d_fb[3]_lut_out, GLOBAL(clk), GLOBAL(reset), , A1L61, , , , );


--d_fb[4] is d_fb[4] at LC_X1_Y24_N0
--operation mode is normal

d_fb[4]_lut_out = d_fb[5];
d_fb[4] = DFFEAS(d_fb[4]_lut_out, GLOBAL(clk), GLOBAL(reset), , A1L61, , , , );


--d_fb[5] is d_fb[5] at LC_X1_Y24_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

d_fb[5]_lut_out = GND;
d_fb[5] = DFFEAS(d_fb[5]_lut_out, GLOBAL(clk), GLOBAL(reset), , A1L61, d_fb[6], , , VCC);


--d_fb[6] is d_fb[6] at LC_X1_Y24_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

d_fb[6]_lut_out = GND;
d_fb[6] = DFFEAS(d_fb[6]_lut_out, GLOBAL(clk), GLOBAL(reset), , A1L61, d_fb[7], , , VCC);


--d_fb[7] is d_fb[7] at LC_X1_Y24_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

d_fb[7]_lut_out = GND;
d_fb[7] = DFFEAS(d_fb[7]_lut_out, GLOBAL(clk), GLOBAL(reset), , A1L61, rxd, , , VCC);


--A1L61 is process7~1 at LC_X1_Y24_N3
--operation mode is normal

A1L61 = scir_v[0] & (!scir_v[1] & scir_v[5]);


--~GND is ~GND at LC_X2_Y21_N2
--operation mode is normal

~GND = GND;


--clk is clk at PIN_28
--operation mode is input

clk = INPUT();


--reset is reset at PIN_16
--operation mode is input

reset = INPUT();


--wr is wr at PIN_20
--operation mode is input

wr = INPUT();


--cs is cs at PIN_3
--operation mode is input

cs = INPUT();


--rd is rd at PIN_14
--operation mode is input

rd = INPUT();


--rxd is rxd at PIN_17
--operation mode is input

rxd = INPUT();


--txd is txd at PIN_19
--operation mode is output

txd = OUTPUT(A1L53);


--rdFULL is rdFULL at PIN_15
--operation mode is output

rdFULL = OUTPUT(rdFULL_s);


--tdEMPTY is tdEMPTY at PIN_18
--operation mode is output

tdEMPTY = OUTPUT(txdF);


--A1L14 is data[0]~7 at PIN_4
--operation mode is bidir

A1L14 = data[0];

--data[0] is data[0] at PIN_4
--operation mode is bidir

data[0]_tri_out = TRI(do_latch[0], A1L55);
data[0] = BIDIR(data[0]_tri_out);


--A1L16 is data[1]~6 at PIN_5
--operation mode is bidir

A1L16 = data[1];

--data[1] is data[1] at PIN_5
--operation mode is bidir

data[1]_tri_out = TRI(do_latch[1], A1L55);
data[1] = BIDIR(data[1]_tri_out);


--A1L18 is data[2]~5 at PIN_6
--operation mode is bidir

A1L18 = data[2];

--data[2] is data[2] at PIN_6
--operation mode is bidir

data[2]_tri_out = TRI(do_latch[2], A1L55);
data[2] = BIDIR(data[2]_tri_out);


--A1L20 is data[3]~4 at PIN_7
--operation mode is bidir

A1L20 = data[3];

--data[3] is data[3] at PIN_7
--operation mode is bidir

data[3]_tri_out = TRI(do_latch[3], A1L55);
data[3] = BIDIR(data[3]_tri_out);


--A1L22 is data[4]~3 at PIN_8
--operation mode is bidir

A1L22 = data[4];

--data[4] is data[4] at PIN_8
--operation mode is bidir

data[4]_tri_out = TRI(do_latch[4], A1L55);
data[4] = BIDIR(data[4]_tri_out);


--A1L24 is data[5]~2 at PIN_11
--operation mode is bidir

A1L24 = data[5];

--data[5] is data[5] at PIN_11
--operation mode is bidir

data[5]_tri_out = TRI(do_latch[5], A1L55);
data[5] = BIDIR(data[5]_tri_out);


--A1L26 is data[6]~1 at PIN_12
--operation mode is bidir

A1L26 = data[6];

--data[6] is data[6] at PIN_12
--operation mode is bidir

data[6]_tri_out = TRI(do_latch[6], A1L55);
data[6] = BIDIR(data[6]_tri_out);


--A1L28 is data[7]~0 at PIN_13
--operation mode is bidir

A1L28 = data[7];

--data[7] is data[7] at PIN_13
--operation mode is bidir

data[7]_tri_out = TRI(do_latch[7], A1L55);
data[7] = BIDIR(data[7]_tri_out);


--A1L68 is rxd~7 at LC_X1_Y23_N4
--operation mode is normal

A1L68 = !rxd;