sci.fit.eqn

VHDL写的SCI接口。quartusII6.0的工程！

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--scit_v[5] is scit_v[5] at LC_X1_Y22_N6
--operation mode is normal

scit_v[5]_carry_eqn = (!A1L100 & A1L104) # (A1L100 & A1L105);
scit_v[5]_lut_out = scit_v[5]_carry_eqn $ scit_v[5];
scit_v[5] = DFFEAS(scit_v[5]_lut_out, GLOBAL(clk), GLOBAL(reset), , , ~GND, , , A1L54);


--scit_v[2] is scit_v[2] at LC_X1_Y22_N3
--operation mode is arithmetic

scit_v[2]_lut_out = scit_v[2] $ !A1L94;
scit_v[2] = DFFEAS(scit_v[2]_lut_out, GLOBAL(clk), GLOBAL(reset), , , A1L60, , , A1L54);

--A1L97 is scit_v[2]~111 at LC_X1_Y22_N3
--operation mode is arithmetic

A1L97_cout_0 = scit_v[2] & !A1L94;
A1L97 = CARRY(A1L97_cout_0);

--A1L98 is scit_v[2]~111COUT1 at LC_X1_Y22_N3
--operation mode is arithmetic

A1L98_cout_1 = scit_v[2] & !A1L95;
A1L98 = CARRY(A1L98_cout_1);


--scit_v[3] is scit_v[3] at LC_X1_Y22_N4
--operation mode is arithmetic

scit_v[3]_lut_out = scit_v[3] $ A1L97;
scit_v[3] = DFFEAS(scit_v[3]_lut_out, GLOBAL(clk), GLOBAL(reset), , , A1L60, , , A1L54);

--A1L100 is scit_v[3]~115 at LC_X1_Y22_N4
--operation mode is arithmetic

A1L100 = A1L101;


--din_latch[4] is din_latch[4] at LC_X1_Y23_N2
--operation mode is normal

din_latch[4]_lut_out = A1L22;
din_latch[4] = DFFEAS(din_latch[4]_lut_out, GLOBAL(wr), VCC, , !cs, , , , );


--A1L48 is Mux~160 at LC_X1_Y23_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

din_latch[6]_qfbk = din_latch[6];
A1L48 = scit_v[3] & (din_latch[6]_qfbk # scit_v[2]) # !scit_v[3] & din_latch[4] & (!scit_v[2]);

--din_latch[6] is din_latch[6] at LC_X1_Y23_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

din_latch[6] = DFFEAS(A1L48, GLOBAL(wr), VCC, , !cs, A1L26, , , VCC);


--din_latch[7] is din_latch[7] at LC_X1_Y23_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

din_latch[7]_lut_out = GND;
din_latch[7] = DFFEAS(din_latch[7]_lut_out, GLOBAL(wr), VCC, , !cs, A1L28, , , VCC);


--A1L49 is Mux~161 at LC_X1_Y23_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

din_latch[5]_qfbk = din_latch[5];
A1L49 = A1L48 & (din_latch[7] # !scit_v[2]) # !A1L48 & scit_v[2] & din_latch[5]_qfbk;

--din_latch[5] is din_latch[5] at LC_X1_Y23_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

din_latch[5] = DFFEAS(A1L49, GLOBAL(wr), VCC, , !cs, A1L24, , , VCC);


--din_latch[0] is din_latch[0] at LC_X2_Y23_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

din_latch[0]_lut_out = GND;
din_latch[0] = DFFEAS(din_latch[0]_lut_out, GLOBAL(wr), VCC, , !cs, A1L14, , , VCC);


--A1L50 is Mux~162 at LC_X1_Y23_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

din_latch[1]_qfbk = din_latch[1];
A1L50 = scit_v[3] & (scit_v[2]) # !scit_v[3] & (scit_v[2] & (din_latch[1]_qfbk) # !scit_v[2] & din_latch[0]);

--din_latch[1] is din_latch[1] at LC_X1_Y23_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

din_latch[1] = DFFEAS(A1L50, GLOBAL(wr), VCC, , !cs, A1L16, , , VCC);


--din_latch[3] is din_latch[3] at LC_X2_Y23_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

din_latch[3]_lut_out = GND;
din_latch[3] = DFFEAS(din_latch[3]_lut_out, GLOBAL(wr), VCC, , !cs, A1L20, , , VCC);


--A1L51 is Mux~163 at LC_X1_Y23_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

din_latch[2]_qfbk = din_latch[2];
A1L51 = A1L50 & (din_latch[3] # !scit_v[3]) # !A1L50 & scit_v[3] & din_latch[2]_qfbk;

--din_latch[2] is din_latch[2] at LC_X1_Y23_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

din_latch[2] = DFFEAS(A1L51, GLOBAL(wr), VCC, , !cs, A1L18, , , VCC);


--scit_v[4] is scit_v[4] at LC_X1_Y22_N5
--operation mode is arithmetic

scit_v[4]_carry_eqn = (!A1L100 & GND) # (A1L100 & VCC);
scit_v[4]_lut_out = scit_v[4] $ !scit_v[4]_carry_eqn;
scit_v[4] = DFFEAS(scit_v[4]_lut_out, GLOBAL(clk), GLOBAL(reset), , , A1L60, , , A1L54);

--A1L104 is scit_v[4]~119 at LC_X1_Y22_N5
--operation mode is arithmetic

A1L104_cout_0 = scit_v[4] & !A1L100;
A1L104 = CARRY(A1L104_cout_0);

--A1L105 is scit_v[4]~119COUT1_133 at LC_X1_Y22_N5
--operation mode is arithmetic

A1L105_cout_1 = scit_v[4] & !A1L100;
A1L105 = CARRY(A1L105_cout_1);


--A1L52 is Mux~164 at LC_X1_Y21_N4
--operation mode is normal

A1L52 = scit_v[4] & scit_v[5] & A1L49 # !scit_v[4] & (A1L51);


--A1L59 is process3~35 at LC_X1_Y22_N8
--operation mode is normal

A1L59 = scit_v[4] & scit_v[3] & scit_v[2];


--A1L53 is Mux~165 at LC_X1_Y21_N2
--operation mode is normal

A1L53 = A1L52 # !A1L59 & !scit_v[5];


--rdFULL_s is rdFULL_s at LC_X1_Y23_N3
--operation mode is normal

rdFULL_s_lut_out = rdFULL_s # A1L87 & rxdF & A1L56;
rdFULL_s = DFFEAS(rdFULL_s_lut_out, GLOBAL(clk), !A1L55, , , , , , );


--txdF is txdF at LC_X1_Y22_N7
--operation mode is normal

txdF_lut_out = A1L58 # txdF # !reset;
txdF = DFFEAS(txdF_lut_out, GLOBAL(clk), !A1L57, , , , , , );


--A1L54 is Mux~166 at LC_X1_Y22_N0
--operation mode is normal

A1L54 = !scit_v[5] & (!scit_v[2] # !scit_v[3] # !scit_v[4]);


--A1L60 is process6~0 at LC_X2_Y22_N2
--operation mode is normal

A1L60 = wr & !txdF;


--scit_v[1] is scit_v[1] at LC_X1_Y22_N2
--operation mode is arithmetic

scit_v[1]_lut_out = scit_v[1] $ (A1L91);
scit_v[1] = DFFEAS(scit_v[1]_lut_out, GLOBAL(clk), GLOBAL(reset), , , ~GND, , , A1L54);

--A1L94 is scit_v[1]~123 at LC_X1_Y22_N2
--operation mode is arithmetic

A1L94_cout_0 = !A1L91 # !scit_v[1];
A1L94 = CARRY(A1L94_cout_0);

--A1L95 is scit_v[1]~123COUT1_132 at LC_X1_Y22_N2
--operation mode is arithmetic

A1L95_cout_1 = !A1L92 # !scit_v[1];
A1L95 = CARRY(A1L95_cout_1);


--rxdF is rxdF at LC_X1_Y23_N7
--operation mode is normal

rxdF_lut_out = rxdF & (!A1L56 # !A1L87) # !rxd;
rxdF = DFFEAS(rxdF_lut_out, GLOBAL(clk), VCC, , , , , , );


--scir_v[2] is scir_v[2] at LC_X2_Y24_N3
--operation mode is arithmetic

scir_v[2]_lut_out = scir_v[2] $ !A1L74;
scir_v[2] = DFFEAS(scir_v[2]_lut_out, GLOBAL(clk), GLOBAL(reset), , , A1L68, , , A1L88);

--A1L77 is scir_v[2]~142 at LC_X2_Y24_N3
--operation mode is arithmetic

A1L77_cout_0 = scir_v[2] & !A1L74;
A1L77 = CARRY(A1L77_cout_0);

--A1L78 is scir_v[2]~142COUT1 at LC_X2_Y24_N3
--operation mode is arithmetic

A1L78_cout_1 = scir_v[2] & !A1L75;
A1L78 = CARRY(A1L78_cout_1);


--scir_v[3] is scir_v[3] at LC_X2_Y24_N4
--operation mode is arithmetic

scir_v[3]_lut_out = scir_v[3] $ A1L77;
scir_v[3] = DFFEAS(scir_v[3]_lut_out, GLOBAL(clk), GLOBAL(reset), , , A1L68, , , A1L88);

--A1L80 is scir_v[3]~146 at LC_X2_Y24_N4
--operation mode is arithmetic

A1L80 = A1L81;


--scir_v[4] is scir_v[4] at LC_X2_Y24_N5
--operation mode is arithmetic

scir_v[4]_carry_eqn = (!A1L80 & GND) # (A1L80 & VCC);
scir_v[4]_lut_out = scir_v[4] $ !scir_v[4]_carry_eqn;
scir_v[4] = DFFEAS(scir_v[4]_lut_out, GLOBAL(clk), GLOBAL(reset), , , A1L68, , , A1L88);

--A1L84 is scir_v[4]~150 at LC_X2_Y24_N5
--operation mode is arithmetic

A1L84_cout_0 = scir_v[4] & !A1L80;
A1L84 = CARRY(A1L84_cout_0);

--A1L85 is scir_v[4]~150COUT1_170 at LC_X2_Y24_N5
--operation mode is arithmetic

A1L85_cout_1 = scir_v[4] & !A1L80;
A1L85 = CARRY(A1L85_cout_1);


--A1L87 is scir_v~153 at LC_X2_Y24_N9
--operation mode is normal

A1L87 = scir_v[2] & scir_v[3] & scir_v[4];


--scir_v[1] is scir_v[1] at LC_X2_Y24_N2
--operation mode is arithmetic

scir_v[1]_lut_out = scir_v[1] $ (A1L71);
scir_v[1] = DFFEAS(scir_v[1]_lut_out, GLOBAL(clk), GLOBAL(reset), , , ~GND, , , A1L88);

--A1L74 is scir_v[1]~155 at LC_X2_Y24_N2
--operation mode is arithmetic

A1L74_cout_0 = !A1L71 # !scir_v[1];
A1L74 = CARRY(A1L74_cout_0);

--A1L75 is scir_v[1]~155COUT1_169 at LC_X2_Y24_N2
--operation mode is arithmetic

A1L75_cout_1 = !A1L72 # !scir_v[1];
A1L75 = CARRY(A1L75_cout_1);


--scir_v[0] is scir_v[0] at LC_X2_Y24_N1
--operation mode is arithmetic

scir_v[0]_lut_out = !scir_v[0];
scir_v[0] = DFFEAS(scir_v[0]_lut_out, GLOBAL(clk), GLOBAL(reset), , , ~GND, , , A1L88);

--A1L71 is scir_v[0]~159 at LC_X2_Y24_N1
--operation mode is arithmetic

A1L71_cout_0 = scir_v[0];
A1L71 = CARRY(A1L71_cout_0);

--A1L72 is scir_v[0]~159COUT1_168 at LC_X2_Y24_N1
--operation mode is arithmetic

A1L72_cout_1 = scir_v[0];
A1L72 = CARRY(A1L72_cout_1);


--scir_v[5] is scir_v[5] at LC_X2_Y24_N6
--operation mode is normal

scir_v[5]_carry_eqn = (!A1L80 & A1L84) # (A1L80 & A1L85);
scir_v[5]_lut_out = scir_v[5]_carry_eqn $ scir_v[5];
scir_v[5] = DFFEAS(scir_v[5]_lut_out, GLOBAL(clk), GLOBAL(reset), , , ~GND, , , A1L88);


--A1L56 is process0~30 at LC_X2_Y24_N0
--operation mode is normal

A1L56 = scir_v[0] & (scir_v[1] & scir_v[5]);


--A1L55 is process0~0 at LC_X1_Y23_N0