sci.map.rpt

VHDL写的SCI接口。quartusII6.0的工程！

; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------+------------------------------+
; sci.vhd                          ; yes             ; Other     ; G:/EDAV new/test_53/sci.vhd  ;
+----------------------------------+-----------------+-----------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 58    ;
;     -- Combinational with no register       ; 19    ;
;     -- Register only                        ; 24    ;
;     -- Combinational with a register        ; 15    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 11    ;
;     -- 3 input functions                    ; 6     ;
;     -- 2 input functions                    ; 13    ;
;     -- 1 input functions                    ; 3     ;
;     -- 0 input functions                    ; 1     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 48    ;
;     -- arithmetic mode                      ; 10    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 12    ;
;     -- asynchronous clear/load mode         ; 22    ;
;                                             ;       ;
; Total registers                             ; 39    ;
; Total logic cells in carry chains           ; 12    ;
; I/O pins                                    ; 17    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 31    ;
; Total fan-out                               ; 243   ;
; Average fan-out                             ; 3.24  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |sci                       ; 58 (58)     ; 39           ; 0           ; 17   ; 0            ; 19 (19)      ; 24 (24)           ; 15 (15)          ; 12 (12)         ; 0 (0)      ; |sci                ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 39    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 12    ;
; Number of registers using Asynchronous Clear ; 22    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 24    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |sci|scir_v[1]             ;
; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |sci|scir_v[4]             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in G:/EDAV new/test_53/sci.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Wed Jun 28 12:13:27 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sci -c sci
Warning: Can't analyze file -- file G:/EDAV new/test44/sci.vhd is missing
Warning: Using design file sci.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: sci-rtl
    Info: Found entity 1: sci
Info: Elaborating entity "sci" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at sci.vhd(71): signal "cs" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at sci.vhd(85): signal "do_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at sci.vhd(151): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at sci.vhd(152): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at sci.vhd(153): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at sci.vhd(154): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at sci.vhd(155): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at sci.vhd(156): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at sci.vhd(157): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at sci.vhd(158): signal "din_latch" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Duplicate registers merged to single register
    Info: Duplicate register "tdEMPTY_s" merged to single register "txdF"
Info: Implemented 75 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 3 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 58 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
    Info: Processing ended: Wed Jun 28 12:13:34 2006
    Info: Elapsed time: 00:00:08