sci.vhd

VHDL写的SCI接口。quartusII6.0的工程！

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY sci IS
   PORT(clk,reset,rxd,rd,wr,cs: IN STD_ULOGIC;
        txd,rdFULL,tdEMPTY    : OUT STD_ULOGIC;
        data                  : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END sci;

ARCHITECTURE rtl OF sci IS
   SIGNAL scir     : STD_ULOGIC_VECTOR(5 DOWNTO 0);
   SIGNAL scit     : STD_ULOGIC_VECTOR(5 DOWNTO 0);
   SIGNAL sh_r     : STD_ULOGIC_VECTOR(3 DOWNTO 0);
   SIGNAL sl_r     : STD_ULOGIC_VECTOR(1 DOWNTO 0);
   SIGNAL sh_t     : STD_ULOGIC_VECTOR(3 DOWNTO 0);
   SIGNAL sl_t     : STD_ULOGIC_VECTOR(1 DOWNTO 0);
   SIGNAL d_fb     : STD_ULOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL din_latch: STD_ULOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL do_latch : STD_ULOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL txdF,rxdF: STD_ULOGIC;
   SIGNAL tdEMPTY_s: STD_ULOGIC:='1';
   SIGNAL rdFULL_s : STD_ULOGIC:='0';

BEGIN
   sh_r<=scir(5 DOWNTO 2); 
   sl_r<=scir(1 DOWNTO 0);
   sh_t<=scit(5 DOWNTO 2);
   sl_t<=scit(1 DOWNTO 0);
   
   tdEMPTY<=tdEMPTY_s;
   rdFULL<=rdFULL_s;
   
   PROCESS(clk,rd,cs)
   BEGIN
      IF(rd='0' AND cs='0') THEN
         rdFULL_s<='0';
      ELSIF(clk'EVENT AND clk='1') THEN
         IF((rxdF='1') AND (sh_r="1111") AND (sl_r="11")) THEN
            do_latch<=d_fb;
            rdFULL_s<='1';
         END IF;
      END IF;
   END PROCESS;

   PROCESS(wr,cs)
      VARIABLE data_v: STD_LOGIC_VECTOR(7 DOWNTO 0);
   BEGIN
      IF(wr'EVENT AND wr='1') THEN
         IF(cs='0') THEN
            data_v:=data;
            din_latch<=TO_STDULOGICVECTOR(data_v);
         END IF;
      END IF;
   END PROCESS;

   PROCESS(clk)
   BEGIN
      IF(rising_edge(clk)) THEN
         IF(rxd='0') THEN
            rxdF<='1';
         ELSIF((rxdF='1') AND (sh_r="1111") AND (sl_r="11")) THEN
            rxdF<='0';
         END IF;
      END IF;
   END PROCESS;

   PROCESS(wr,clk)
   BEGIN
      IF(wr='0' AND cs='0') THEN
         txdF<='0';
         tdEMPTY_s<='0';
      ELSIF(rising_edge(clk)) THEN
         IF(((txdF='0') AND(sh_t="1111") AND (sl_t="11")) OR reset='0') THEN
            tdEMPTY_s<='1';
            txdF<='1'; 
         END IF;
      END IF;
   END PROCESS;

   PROCESS(rd,cs)
      VARIABLE do_latch_v: STD_ULOGIC_VECTOR(7 DOWNTO 0);
   BEGIN
      do_latch_v:=do_latch;
      IF(rd='0' AND cs='0') THEN
         data<=TO_STDLOGICVECTOR(do_latch_v);
      ELSE
         data<="ZZZZZZZZ";
      END IF;
   END PROCESS;

   PROCESS(clk,reset)
      VARIABLE scir_v: INTEGER RANGE 0 TO 63;
      VARIABLE scir_s: STD_LOGIC_VECTOR(5 DOWNTO 0);
   BEGIN
      IF(reset='0') THEN
         scir_v:=0;
      ELSIF(rising_edge(clk)) THEN
         IF((scir_v<=27) AND (rxd='0')) THEN
            scir_v:=28;
         ELSIF((scir_v<=27) AND (rxd='1')) THEN
            scir_v:=0;
         ELSE
            scir_v:=scir_v+1;
         END IF;
      END IF;
      scir_s:=CONV_STD_LOGIC_VECTOR(scir_v,6);
      scir<=TO_STDULOGICVECTOR(scir_s);
   END PROCESS;

   PROCESS(clk,reset)
      VARIABLE scit_v: INTEGER RANGE 0 TO 63;
      VARIABLE scit_s: STD_LOGIC_VECTOR(5 DOWNTO 0);
   BEGIN
      IF(reset='0') THEN
         scit_v:=0;
      ELSIF(rising_edge(clk)) THEN
         IF(scit_v<=27) THEN
            IF(tdEMPTY_s='0' AND wr='1') THEN
               scit_v:=28;
            ELSE
               scit_v:=0;
            END IF;
         ELSE
            scit_v:=scit_v+1;
         END IF;
      END IF;
      scit_s:=CONV_STD_LOGIC_VECTOR(scit_v,6);
      scit<=TO_STDULOGICVECTOR(scit_s);
   END PROCESS;

   PROCESS(clk,reset)
   BEGIN
      IF(reset='0') THEN
         d_fb<="00000000";
      ELSIF(rising_edge(clk)) THEN
         IF((sh_r>="1000") AND (sh_r<="1111") AND (sl_r="01")) THEN
            d_fb(7)<=rxd;
            FOR i IN 0 TO 6 LOOP
              d_fb(i)<=d_fb(i+1);
            END LOOP;
         END IF;
      END IF;
   END PROCESS;
  
   PROCESS(sh_t)    
   BEGIN
      CASE sh_t IS
         WHEN "0111"=>txd<='0';
         WHEN "1000"=>txd<=din_latch(0);
         WHEN "1001"=>txd<=din_latch(1);
         WHEN "1010"=>txd<=din_latch(2);
         WHEN "1011"=>txd<=din_latch(3);
         WHEN "1100"=>txd<=din_latch(4);
         WHEN "1101"=>txd<=din_latch(5);
         WHEN "1110"=>txd<=din_latch(6);
         WHEN "1111"=>txd<=din_latch(7);
         WHEN OTHERS=>txd<='1';
      END CASE;
   END PROCESS;

END rtl;