sci.map.eqn

VHDL写的SCI接口。quartusII6.0的工程！

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--scit_v[5] is scit_v[5]
--operation mode is normal

scit_v[5]_carry_eqn = A1L93;
scit_v[5]_lut_out = scit_v[5] $ (scit_v[5]_carry_eqn);
scit_v[5] = DFFEAS(scit_v[5]_lut_out, clk, reset, , , ~GND, , , A1L54);


--din_latch[5] is din_latch[5]
--operation mode is normal

din_latch[5]_lut_out = A1L24;
din_latch[5] = DFFEAS(din_latch[5]_lut_out, wr, VCC, , !cs, , , , );


--scit_v[2] is scit_v[2]
--operation mode is arithmetic

scit_v[2]_carry_eqn = A1L87;
scit_v[2]_lut_out = scit_v[2] $ (!scit_v[2]_carry_eqn);
scit_v[2] = DFFEAS(scit_v[2]_lut_out, clk, reset, , , A1L60, , , A1L54);

--A1L89 is scit_v[2]~111
--operation mode is arithmetic

A1L89 = CARRY(scit_v[2] & (!A1L87));


--din_latch[6] is din_latch[6]
--operation mode is normal

din_latch[6]_lut_out = A1L26;
din_latch[6] = DFFEAS(din_latch[6]_lut_out, wr, VCC, , !cs, , , , );


--scit_v[3] is scit_v[3]
--operation mode is arithmetic

scit_v[3]_carry_eqn = A1L89;
scit_v[3]_lut_out = scit_v[3] $ (scit_v[3]_carry_eqn);
scit_v[3] = DFFEAS(scit_v[3]_lut_out, clk, reset, , , A1L60, , , A1L54);

--A1L91 is scit_v[3]~115
--operation mode is arithmetic

A1L91 = CARRY(!A1L89 # !scit_v[3]);


--din_latch[4] is din_latch[4]
--operation mode is normal

din_latch[4]_lut_out = A1L22;
din_latch[4] = DFFEAS(din_latch[4]_lut_out, wr, VCC, , !cs, , , , );


--A1L48 is Mux~160
--operation mode is normal

A1L48 = scit_v[2] & (scit_v[3]) # !scit_v[2] & (scit_v[3] & din_latch[6] # !scit_v[3] & (din_latch[4]));


--din_latch[7] is din_latch[7]
--operation mode is normal

din_latch[7]_lut_out = A1L28;
din_latch[7] = DFFEAS(din_latch[7]_lut_out, wr, VCC, , !cs, , , , );


--A1L49 is Mux~161
--operation mode is normal

A1L49 = scit_v[2] & (A1L48 & (din_latch[7]) # !A1L48 & din_latch[5]) # !scit_v[2] & (A1L48);


--din_latch[2] is din_latch[2]
--operation mode is normal

din_latch[2]_lut_out = A1L18;
din_latch[2] = DFFEAS(din_latch[2]_lut_out, wr, VCC, , !cs, , , , );


--din_latch[1] is din_latch[1]
--operation mode is normal

din_latch[1]_lut_out = A1L16;
din_latch[1] = DFFEAS(din_latch[1]_lut_out, wr, VCC, , !cs, , , , );


--din_latch[0] is din_latch[0]
--operation mode is normal

din_latch[0]_lut_out = A1L14;
din_latch[0] = DFFEAS(din_latch[0]_lut_out, wr, VCC, , !cs, , , , );


--A1L50 is Mux~162
--operation mode is normal

A1L50 = scit_v[3] & (scit_v[2]) # !scit_v[3] & (scit_v[2] & din_latch[1] # !scit_v[2] & (din_latch[0]));


--din_latch[3] is din_latch[3]
--operation mode is normal

din_latch[3]_lut_out = A1L20;
din_latch[3] = DFFEAS(din_latch[3]_lut_out, wr, VCC, , !cs, , , , );


--A1L51 is Mux~163
--operation mode is normal

A1L51 = scit_v[3] & (A1L50 & (din_latch[3]) # !A1L50 & din_latch[2]) # !scit_v[3] & (A1L50);


--scit_v[4] is scit_v[4]
--operation mode is arithmetic

scit_v[4]_carry_eqn = A1L91;
scit_v[4]_lut_out = scit_v[4] $ (!scit_v[4]_carry_eqn);
scit_v[4] = DFFEAS(scit_v[4]_lut_out, clk, reset, , , A1L60, , , A1L54);

--A1L93 is scit_v[4]~119
--operation mode is arithmetic

A1L93 = CARRY(scit_v[4] & (!A1L91));


--A1L52 is Mux~164
--operation mode is normal

A1L52 = scit_v[4] & scit_v[5] & A1L49 # !scit_v[4] & (A1L51);


--A1L59 is process3~35
--operation mode is normal

A1L59 = scit_v[4] & scit_v[3] & scit_v[2];


--A1L53 is Mux~165
--operation mode is normal

A1L53 = A1L52 # !scit_v[5] & !A1L59;


--rdFULL_s is rdFULL_s
--operation mode is normal

rdFULL_s_lut_out = rdFULL_s # rxdF & A1L81 & A1L56;
rdFULL_s = DFFEAS(rdFULL_s_lut_out, clk, !A1L55, , , , , , );


--txdF is txdF
--operation mode is normal

txdF_lut_out = txdF # A1L58 # !reset;
txdF = DFFEAS(txdF_lut_out, clk, !A1L57, , , , , , );


--A1L54 is Mux~166
--operation mode is normal

A1L54 = !scit_v[5] & (!scit_v[2] # !scit_v[3] # !scit_v[4]);


--A1L60 is process6~0
--operation mode is normal

A1L60 = wr & (!txdF);


--scit_v[1] is scit_v[1]
--operation mode is arithmetic

scit_v[1]_carry_eqn = A1L85;
scit_v[1]_lut_out = scit_v[1] $ (scit_v[1]_carry_eqn);
scit_v[1] = DFFEAS(scit_v[1]_lut_out, clk, reset, , , ~GND, , , A1L54);

--A1L87 is scit_v[1]~123
--operation mode is arithmetic

A1L87 = CARRY(!A1L85 # !scit_v[1]);


--rxdF is rxdF
--operation mode is normal

rxdF_lut_out = rxdF & (!A1L56 # !A1L81) # !rxd;
rxdF = DFFEAS(rxdF_lut_out, clk, VCC, , , , , , );


--scir_v[2] is scir_v[2]
--operation mode is arithmetic

scir_v[2]_carry_eqn = A1L73;
scir_v[2]_lut_out = scir_v[2] $ (!scir_v[2]_carry_eqn);
scir_v[2] = DFFEAS(scir_v[2]_lut_out, clk, reset, , , A1L68, , , A1L82);

--A1L75 is scir_v[2]~142
--operation mode is arithmetic

A1L75 = CARRY(scir_v[2] & (!A1L73));


--scir_v[3] is scir_v[3]
--operation mode is arithmetic

scir_v[3]_carry_eqn = A1L75;
scir_v[3]_lut_out = scir_v[3] $ (scir_v[3]_carry_eqn);
scir_v[3] = DFFEAS(scir_v[3]_lut_out, clk, reset, , , A1L68, , , A1L82);

--A1L77 is scir_v[3]~146
--operation mode is arithmetic

A1L77 = CARRY(!A1L75 # !scir_v[3]);


--scir_v[4] is scir_v[4]
--operation mode is arithmetic

scir_v[4]_carry_eqn = A1L77;
scir_v[4]_lut_out = scir_v[4] $ (!scir_v[4]_carry_eqn);
scir_v[4] = DFFEAS(scir_v[4]_lut_out, clk, reset, , , A1L68, , , A1L82);

--A1L79 is scir_v[4]~150
--operation mode is arithmetic

A1L79 = CARRY(scir_v[4] & (!A1L77));


--A1L81 is scir_v~153
--operation mode is normal

A1L81 = scir_v[2] & scir_v[3] & scir_v[4];


--scir_v[1] is scir_v[1]
--operation mode is arithmetic

scir_v[1]_carry_eqn = A1L71;
scir_v[1]_lut_out = scir_v[1] $ (scir_v[1]_carry_eqn);
scir_v[1] = DFFEAS(scir_v[1]_lut_out, clk, reset, , , ~GND, , , A1L82);

--A1L73 is scir_v[1]~155
--operation mode is arithmetic

A1L73 = CARRY(!A1L71 # !scir_v[1]);


--scir_v[0] is scir_v[0]
--operation mode is arithmetic

scir_v[0]_lut_out = !scir_v[0];
scir_v[0] = DFFEAS(scir_v[0]_lut_out, clk, reset, , , ~GND, , , A1L82);

--A1L71 is scir_v[0]~159
--operation mode is arithmetic

A1L71 = CARRY(scir_v[0]);


--scir_v[5] is scir_v[5]
--operation mode is normal

scir_v[5]_carry_eqn = A1L79;
scir_v[5]_lut_out = scir_v[5] $ (scir_v[5]_carry_eqn);
scir_v[5] = DFFEAS(scir_v[5]_lut_out, clk, reset, , , ~GND, , , A1L82);


--A1L56 is process0~30
--operation mode is normal

A1L56 = scir_v[1] & scir_v[0] & scir_v[5];


--A1L55 is process0~0
--operation mode is normal

A1L55 = !cs & !rd;


--scit_v[0] is scit_v[0]
--operation mode is arithmetic

scit_v[0]_lut_out = !scit_v[0];
scit_v[0] = DFFEAS(scit_v[0]_lut_out, clk, reset, , , ~GND, , , A1L54);

--A1L85 is scit_v[0]~127
--operation mode is arithmetic

A1L85 = CARRY(scit_v[0]);


--A1L58 is process3~2
--operation mode is normal

A1L58 = scit_v[5] & scit_v[1] & scit_v[0] & A1L59;


--A1L57 is process3~0
--operation mode is normal

A1L57 = !wr & !cs;


--A1L82 is scir_v~166
--operation mode is normal

A1L82 = !scir_v[5] & (!scir_v[4] # !scir_v[3] # !scir_v[2]);


--do_latch[0] is do_latch[0]
--operation mode is normal

do_latch[0]_lut_out = d_fb[0];
do_latch[0] = DFFEAS(do_latch[0]_lut_out, clk, VCC, , A1L40, , , , );


--do_latch[1] is do_latch[1]
--operation mode is normal

do_latch[1]_lut_out = d_fb[1];
do_latch[1] = DFFEAS(do_latch[1]_lut_out, clk, VCC, , A1L40, , , , );


--do_latch[2] is do_latch[2]
--operation mode is normal

do_latch[2]_lut_out = d_fb[2];
do_latch[2] = DFFEAS(do_latch[2]_lut_out, clk, VCC, , A1L40, , , , );


--do_latch[3] is do_latch[3]
--operation mode is normal

do_latch[3]_lut_out = d_fb[3];
do_latch[3] = DFFEAS(do_latch[3]_lut_out, clk, VCC, , A1L40, , , , );


--do_latch[4] is do_latch[4]
--operation mode is normal

do_latch[4]_lut_out = d_fb[4];
do_latch[4] = DFFEAS(do_latch[4]_lut_out, clk, VCC, , A1L40, , , , );


--do_latch[5] is do_latch[5]
--operation mode is normal

do_latch[5]_lut_out = d_fb[5];
do_latch[5] = DFFEAS(do_latch[5]_lut_out, clk, VCC, , A1L40, , , , );


--do_latch[6] is do_latch[6]
--operation mode is normal

do_latch[6]_lut_out = d_fb[6];
do_latch[6] = DFFEAS(do_latch[6]_lut_out, clk, VCC, , A1L40, , , , );


--do_latch[7] is do_latch[7]
--operation mode is normal

do_latch[7]_lut_out = d_fb[7];
do_latch[7] = DFFEAS(do_latch[7]_lut_out, clk, VCC, , A1L40, , , , );


--d_fb[0] is d_fb[0]
--operation mode is normal

d_fb[0]_lut_out = d_fb[1];
d_fb[0] = DFFEAS(d_fb[0]_lut_out, clk, reset, , A1L61, , , , );


--A1L40 is do_latch[0]~7
--operation mode is normal

A1L40 = rxdF & A1L81 & A1L56 & !A1L55;


--d_fb[1] is d_fb[1]
--operation mode is normal

d_fb[1]_lut_out = d_fb[2];
d_fb[1] = DFFEAS(d_fb[1]_lut_out, clk, reset, , A1L61, , , , );


--d_fb[2] is d_fb[2]
--operation mode is normal

d_fb[2]_lut_out = d_fb[3];
d_fb[2] = DFFEAS(d_fb[2]_lut_out, clk, reset, , A1L61, , , , );


--d_fb[3] is d_fb[3]
--operation mode is normal

d_fb[3]_lut_out = d_fb[4];
d_fb[3] = DFFEAS(d_fb[3]_lut_out, clk, reset, , A1L61, , , , );


--d_fb[4] is d_fb[4]
--operation mode is normal

d_fb[4]_lut_out = d_fb[5];
d_fb[4] = DFFEAS(d_fb[4]_lut_out, clk, reset, , A1L61, , , , );


--d_fb[5] is d_fb[5]
--operation mode is normal

d_fb[5]_lut_out = d_fb[6];
d_fb[5] = DFFEAS(d_fb[5]_lut_out, clk, reset, , A1L61, , , , );


--d_fb[6] is d_fb[6]
--operation mode is normal

d_fb[6]_lut_out = d_fb[7];
d_fb[6] = DFFEAS(d_fb[6]_lut_out, clk, reset, , A1L61, , , , );


--d_fb[7] is d_fb[7]
--operation mode is normal

d_fb[7]_lut_out = rxd;
d_fb[7] = DFFEAS(d_fb[7]_lut_out, clk, reset, , A1L61, , , , );


--A1L61 is process7~1
--operation mode is normal

A1L61 = scir_v[0] & scir_v[5] & (!scir_v[1]);


--~GND is ~GND
--operation mode is normal

~GND = GND;


--clk is clk
--operation mode is input

clk = INPUT();


--reset is reset
--operation mode is input

reset = INPUT();


--wr is wr
--operation mode is input

wr = INPUT();


--cs is cs
--operation mode is input

cs = INPUT();


--rd is rd
--operation mode is input

rd = INPUT();


--rxd is rxd
--operation mode is input

rxd = INPUT();


--txd is txd
--operation mode is output

txd = OUTPUT(A1L53);


--rdFULL is rdFULL
--operation mode is output

rdFULL = OUTPUT(rdFULL_s);


--tdEMPTY is tdEMPTY
--operation mode is output

tdEMPTY = OUTPUT(txdF);


--A1L14 is data[0]~7
--operation mode is bidir

A1L14 = data[0];

--data[0] is data[0]
--operation mode is bidir

data[0]_tri_out = TRI(do_latch[0], A1L55);
data[0] = BIDIR(data[0]_tri_out);


--A1L16 is data[1]~6
--operation mode is bidir

A1L16 = data[1];

--data[1] is data[1]
--operation mode is bidir

data[1]_tri_out = TRI(do_latch[1], A1L55);
data[1] = BIDIR(data[1]_tri_out);


--A1L18 is data[2]~5
--operation mode is bidir

A1L18 = data[2];

--data[2] is data[2]
--operation mode is bidir

data[2]_tri_out = TRI(do_latch[2], A1L55);
data[2] = BIDIR(data[2]_tri_out);


--A1L20 is data[3]~4
--operation mode is bidir

A1L20 = data[3];

--data[3] is data[3]
--operation mode is bidir

data[3]_tri_out = TRI(do_latch[3], A1L55);
data[3] = BIDIR(data[3]_tri_out);


--A1L22 is data[4]~3
--operation mode is bidir

A1L22 = data[4];

--data[4] is data[4]
--operation mode is bidir

data[4]_tri_out = TRI(do_latch[4], A1L55);
data[4] = BIDIR(data[4]_tri_out);


--A1L24 is data[5]~2
--operation mode is bidir

A1L24 = data[5];

--data[5] is data[5]
--operation mode is bidir

data[5]_tri_out = TRI(do_latch[5], A1L55);
data[5] = BIDIR(data[5]_tri_out);


--A1L26 is data[6]~1
--operation mode is bidir

A1L26 = data[6];

--data[6] is data[6]
--operation mode is bidir

data[6]_tri_out = TRI(do_latch[6], A1L55);
data[6] = BIDIR(data[6]_tri_out);


--A1L28 is data[7]~0
--operation mode is bidir

A1L28 = data[7];

--data[7] is data[7]
--operation mode is bidir

data[7]_tri_out = TRI(do_latch[7], A1L55);
data[7] = BIDIR(data[7]_tri_out);


--A1L68 is rxd~7
--operation mode is normal

A1L68 = !rxd;