sci.tan.rpt

VHDL写的SCI接口。quartusII6.0的工程！

; N/A           ; None        ; -7.178 ns ; cs      ; do_latch[4]  ; clk      ;
; N/A           ; None        ; -7.178 ns ; cs      ; do_latch[6]  ; clk      ;
; N/A           ; None        ; -7.178 ns ; cs      ; do_latch[7]  ; clk      ;
; N/A           ; None        ; -7.178 ns ; cs      ; do_latch[5]  ; clk      ;
; N/A           ; None        ; -7.178 ns ; cs      ; do_latch[3]  ; clk      ;
; N/A           ; None        ; -7.178 ns ; cs      ; do_latch[2]  ; clk      ;
; N/A           ; None        ; -7.416 ns ; rd      ; do_latch[4]  ; clk      ;
; N/A           ; None        ; -7.416 ns ; rd      ; do_latch[6]  ; clk      ;
; N/A           ; None        ; -7.416 ns ; rd      ; do_latch[7]  ; clk      ;
; N/A           ; None        ; -7.416 ns ; rd      ; do_latch[5]  ; clk      ;
; N/A           ; None        ; -7.416 ns ; rd      ; do_latch[3]  ; clk      ;
; N/A           ; None        ; -7.416 ns ; rd      ; do_latch[2]  ; clk      ;
+---------------+-------------+-----------+---------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Wed Jun 28 12:14:07 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sci -c sci --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "wr" is an undefined clock
Info: Clock "clk" has Internal fmax of 239.29 MHz between source register "rxdF" and destination register "do_latch[2]" (period= 4.179 ns)
    Info: + Longest register to register delay is 3.918 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y23_N7; Fanout = 3; REG Node = 'rxdF'
        Info: 2: + IC(1.267 ns) + CELL(0.590 ns) = 1.857 ns; Loc. = LC_X2_Y24_N7; Fanout = 8; COMB Node = 'do_latch[0]~7'
        Info: 3: + IC(1.194 ns) + CELL(0.867 ns) = 3.918 ns; Loc. = LC_X1_Y25_N6; Fanout = 1; REG Node = 'do_latch[2]'
        Info: Total cell delay = 1.457 ns ( 37.19 % )
        Info: Total interconnect delay = 2.461 ns ( 62.81 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.245 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 31; CLK Node = 'clk'
            Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X1_Y25_N6; Fanout = 1; REG Node = 'do_latch[2]'
            Info: Total cell delay = 2.180 ns ( 67.18 % )
            Info: Total interconnect delay = 1.065 ns ( 32.82 % )
        Info: - Longest clock path from clock "clk" to source register is 3.245 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 31; CLK Node = 'clk'
            Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X1_Y23_N7; Fanout = 3; REG Node = 'rxdF'
            Info: Total cell delay = 2.180 ns ( 67.18 % )
            Info: Total interconnect delay = 1.065 ns ( 32.82 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: No valid register-to-register data paths exist for clock "wr"
Info: tsu for register "do_latch[4]" (data pin = "rd", clock pin = "clk") is 7.468 ns
    Info: + Longest pin to register delay is 10.676 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_14; Fanout = 1; PIN Node = 'rd'
        Info: 2: + IC(5.062 ns) + CELL(0.442 ns) = 6.973 ns; Loc. = LC_X1_Y23_N0; Fanout = 10; COMB Node = 'process0~0'
        Info: 3: + IC(1.200 ns) + CELL(0.442 ns) = 8.615 ns; Loc. = LC_X2_Y24_N7; Fanout = 8; COMB Node = 'do_latch[0]~7'
        Info: 4: + IC(1.194 ns) + CELL(0.867 ns) = 10.676 ns; Loc. = LC_X1_Y25_N2; Fanout = 1; REG Node = 'do_latch[4]'
        Info: Total cell delay = 3.220 ns ( 30.16 % )
        Info: Total interconnect delay = 7.456 ns ( 69.84 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.245 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 31; CLK Node = 'clk'
        Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X1_Y25_N2; Fanout = 1; REG Node = 'do_latch[4]'
        Info: Total cell delay = 2.180 ns ( 67.18 % )
        Info: Total interconnect delay = 1.065 ns ( 32.82 % )
Info: tco from clock "wr" to destination pin "txd" through register "din_latch[4]" is 19.337 ns
    Info: + Longest clock path from clock "wr" to source register is 11.251 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_20; Fanout = 10; CLK Node = 'wr'
        Info: 2: + IC(9.071 ns) + CELL(0.711 ns) = 11.251 ns; Loc. = LC_X1_Y23_N2; Fanout = 1; REG Node = 'din_latch[4]'
        Info: Total cell delay = 2.180 ns ( 19.38 % )
        Info: Total interconnect delay = 9.071 ns ( 80.62 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 7.862 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y23_N2; Fanout = 1; REG Node = 'din_latch[4]'
        Info: 2: + IC(0.540 ns) + CELL(0.590 ns) = 1.130 ns; Loc. = LC_X1_Y23_N9; Fanout = 1; COMB Node = 'Mux~160'
        Info: 3: + IC(0.440 ns) + CELL(0.590 ns) = 2.160 ns; Loc. = LC_X1_Y23_N8; Fanout = 1; COMB Node = 'Mux~161'
        Info: 4: + IC(1.192 ns) + CELL(0.442 ns) = 3.794 ns; Loc. = LC_X1_Y21_N4; Fanout = 1; COMB Node = 'Mux~164'
        Info: 5: + IC(0.407 ns) + CELL(0.442 ns) = 4.643 ns; Loc. = LC_X1_Y21_N2; Fanout = 1; COMB Node = 'Mux~165'
        Info: 6: + IC(1.095 ns) + CELL(2.124 ns) = 7.862 ns; Loc. = PIN_19; Fanout = 0; PIN Node = 'txd'
        Info: Total cell delay = 4.188 ns ( 53.27 % )
        Info: Total interconnect delay = 3.674 ns ( 46.73 % )
Info: Longest tpd from source pin "rd" to destination pin "data[2]" is 10.771 ns
    Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_14; Fanout = 1; PIN Node = 'rd'
    Info: 2: + IC(5.062 ns) + CELL(0.442 ns) = 6.973 ns; Loc. = LC_X1_Y23_N0; Fanout = 10; COMB Node = 'process0~0'
    Info: 3: + IC(1.724 ns) + CELL(2.074 ns) = 10.771 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'data[2]'
    Info: Total cell delay = 3.985 ns ( 37.00 % )
    Info: Total interconnect delay = 6.786 ns ( 63.00 % )
Info: th for register "din_latch[6]" (data pin = "data[6]", clock pin = "wr") is 5.092 ns
    Info: + Longest clock path from clock "wr" to destination register is 11.251 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_20; Fanout = 10; CLK Node = 'wr'
        Info: 2: + IC(9.071 ns) + CELL(0.711 ns) = 11.251 ns; Loc. = LC_X1_Y23_N9; Fanout = 1; REG Node = 'din_latch[6]'
        Info: Total cell delay = 2.180 ns ( 19.38 % )
        Info: Total interconnect delay = 9.071 ns ( 80.62 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 6.174 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_12; Fanout = 1; PIN Node = 'data[6]'
        Info: 2: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = IOC_X0_Y23_N1; Fanout = 1; COMB Node = 'data[6]~1'
        Info: 3: + IC(4.590 ns) + CELL(0.115 ns) = 6.174 ns; Loc. = LC_X1_Y23_N9; Fanout = 1; REG Node = 'din_latch[6]'
        Info: Total cell delay = 1.584 ns ( 25.66 % )
        Info: Total interconnect delay = 4.590 ns ( 74.34 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Jun 28 12:14:09 2006
    Info: Elapsed time: 00:00:04