lcd1.map.qmsg

通过VHDL写的128*32液晶驱动接口。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 24 22:29:22 2008 " "Info: Processing started: Sat May 24 22:29:22 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lcd1 -c lcd1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcd1 -c lcd1" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"FREE_COUNTER\";  expecting \"begin\", or a declaration statement,  lcd1.vhd(18) " "Error (10500): VHDL syntax error at lcd1.vhd(18) near text \"FREE_COUNTER\";  expecting \"begin\", or a declaration statement, " {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd2/lcd1.vhd" 18 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"BLOCK\";  expecting \"process\" lcd1.vhd(24) " "Error (10500): VHDL syntax error at lcd1.vhd(24) near text \"BLOCK\";  expecting \"process\"" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd2/lcd1.vhd" 24 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"BLOCK\";  expecting \"(\", or an identifier (\"block\" is a reserved keyword), or a sequential statement,  lcd1.vhd(26) " "Error (10500): VHDL syntax error at lcd1.vhd(26) near text \"BLOCK\";  expecting \"(\", or an identifier (\"block\" is a reserved keyword), or a sequential statement, " {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd2/lcd1.vhd" 26 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"OUT\";  expecting \"(\", or an identifier (\"out\" is a reserved keyword), or a sequential statement,  lcd1.vhd(40) " "Error (10500): VHDL syntax error at lcd1.vhd(40) near text \"OUT\";  expecting \"(\", or an identifier (\"out\" is a reserved keyword), or a sequential statement, " {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd2/lcd1.vhd" 40 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\")\";  expecting \"(\", or \"'\", or \".\" lcd1.vhd(40) " "Error (10500): VHDL syntax error at lcd1.vhd(40) near text \")\";  expecting \"(\", or \"'\", or \".\"" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd2/lcd1.vhd" 40 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"GENERIC\";  expecting \"(\", or \"'\", or \".\" lcd1.vhd(44) " "Error (10500): VHDL syntax error at lcd1.vhd(44) near text \"GENERIC\";  expecting \"(\", or \"'\", or \".\"" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd2/lcd1.vhd" 44 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"PORT\";  expecting \":=\", or \"<=\" lcd1.vhd(52) " "Error (10500): VHDL syntax error at lcd1.vhd(52) near text \"PORT\";  expecting \":=\", or \"<=\"" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd2/lcd1.vhd" 52 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\";\";  expecting \":=\", or \"<=\" lcd1.vhd(57) " "Error (10500): VHDL syntax error at lcd1.vhd(57) near text \";\";  expecting \":=\", or \"<=\"" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd2/lcd1.vhd" 57 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"begin\";  expecting \":=\", or \"<=\" lcd1.vhd(59) " "Error (10500): VHDL syntax error at lcd1.vhd(59) near text \"begin\";  expecting \":=\", or \"<=\"" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd2/lcd1.vhd" 59 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"BLOCK\";  expecting \";\", or an identifier (\"block\" is a reserved keyword), or \"architecture\" lcd1.vhd(64) " "Error (10500): VHDL syntax error at lcd1.vhd(64) near text \"BLOCK\";  expecting \";\", or an identifier (\"block\" is a reserved keyword), or \"architecture\"" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd2/lcd1.vhd" 64 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd1.vhd 0 0 " "Info: Found 0 design units, including 0 entities, in source file lcd1.vhd" {  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 10 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 10 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Sat May 24 22:29:22 2008 " "Error: Processing ended: Sat May 24 22:29:22 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}