lcd1.vhd

通过VHDL写的128*32液晶驱动接口。

LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY lcd1 IS
	PORT
	(
		clk,RST: IN STD_LOGIC ;
		oe,BUSY	: IN STD_LOGIC ;
		STOBE	: OUT STD_LOGIC;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END lcd1;
ARCHITECTURE SYN OF lcd1 IS
	SIGNAL sub_wire0,ADDRESS	: STD_LOGIC_VECTOR (7 DOWNTO 0);
	SIGNAL INCLOCK,OUTCLOCK:STD_LOGIC;

FREE_COUNTER:BLOCK
BEGIN
P1:	PROCESS(CLK,RST)
	BEGIN
	

END BLOCK FREE_COUNTER;	

ROM:BLOCK
	COMPONENT lpm_rom
	GENERIC (
		lpm_width		: NATURAL;
		lpm_widthad		: NATURAL;
		lpm_address_control		: STRING;
		lpm_outdata		: STRING;
		lpm_file		: STRING;
		lpm_type		: STRING
	);
	PORT (
			outclock	: IN STD_LOGIC ;
			address	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
			inclock	: IN STD_LOGIC ;
			q	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
	END COMPONENT;
BEGIN
	lpm_rom_component : lpm_rom
	GENERIC MAP (
		lpm_width => 8,
		lpm_widthad => 8,
		lpm_address_control => "REGISTERED",
		lpm_outdata => "REGISTERED",
		lpm_file => "lcd1.mif",
		lpm_type => "LPM_ROM"
	)
	PORT MAP (
		outclock => outclock,
		address => address,
		inclock => inclock,
		q => sub_wire0
	);
process(oe)
begin
	if oe='0' then
  		q    <= sub_wire0(7 DOWNTO 0);
	end if;
end process;
END BLOCK ROM;
END SYN;