lcd1.map.qmsg

通过VHDL写的128*32液晶驱动接口。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 24 22:27:37 2008 " "Info: Processing started: Sat May 24 22:27:37 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lcd1 -c lcd1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcd1 -c lcd1" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom " "Info: Found design unit 1: rom" {  } { { "rom.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/rom.vhd" 4 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lcd1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lcd1-beha " "Info: Found design unit 1: lcd1-beha" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lcd1 " "Info: Found entity 1: lcd1" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lcd1 " "Info: Elaborating entity \"lcd1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "data\[1\]~reg0 data_in GND " "Warning: Reduced register \"data\[1\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "data\[0\]~reg0 High " "Info: Power-up level of register \"data\[0\]~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "data\[0\]~reg0 data_in VCC " "Warning: Reduced register \"data\[0\]~reg0\" with stuck data_in port to stuck value VCC" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "data\[2\]~reg0 data_in GND " "Warning: Reduced register \"data\[2\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "data\[3\]~reg0 data_in GND " "Warning: Reduced register \"data\[3\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "data\[4\]~reg0 High " "Info: Power-up level of register \"data\[4\]~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "data\[4\]~reg0 data_in VCC " "Warning: Reduced register \"data\[4\]~reg0\" with stuck data_in port to stuck value VCC" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "data\[5\]~reg0 data_in GND " "Warning: Reduced register \"data\[5\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "data\[6\]~reg0 data_in GND " "Warning: Reduced register \"data\[6\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "data\[7\]~reg0 data_in GND " "Warning: Reduced register \"data\[7\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "st data\[0\]~en " "Info: Duplicate register \"st\" merged to single register \"data\[0\]~en\"" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[1\]~en data\[0\]~en " "Info: Duplicate register \"data\[1\]~en\" merged to single register \"data\[0\]~en\"" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[2\]~en data\[0\]~en " "Info: Duplicate register \"data\[2\]~en\" merged to single register \"data\[0\]~en\"" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[3\]~en data\[0\]~en " "Info: Duplicate register \"data\[3\]~en\" merged to single register \"data\[0\]~en\"" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[4\]~en data\[0\]~en " "Info: Duplicate register \"data\[4\]~en\" merged to single register \"data\[0\]~en\"" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[5\]~en data\[0\]~en " "Info: Duplicate register \"data\[5\]~en\" merged to single register \"data\[0\]~en\"" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[6\]~en data\[0\]~en " "Info: Duplicate register \"data\[6\]~en\" merged to single register \"data\[0\]~en\"" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[7\]~en data\[0\]~en " "Info: Duplicate register \"data\[7\]~en\" merged to single register \"data\[0\]~en\"" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "12 " "Info: Implemented 12 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "1 " "Info: Implemented 1 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 24 22:27:39 2008 " "Info: Processing ended: Sat May 24 22:27:39 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}