lcd1.tan.qmsg

通过VHDL写的128*32液晶驱动接口。

{ "Info" "ITDB_TSU_RESULT" "data\[0\]~en BUSY clk 2.466 ns register " "Info: tsu for register \"data\[0\]~en\" (data pin = \"BUSY\", clock pin = \"clk\") is 2.466 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.680 ns + Longest pin register " "Info: + Longest pin to register delay is 6.680 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns BUSY 1 PIN PIN_45 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_45; Fanout = 1; PIN Node = 'BUSY'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { BUSY } "NODE_NAME" } } { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.096 ns) + CELL(0.115 ns) 6.680 ns data\[0\]~en 2 REG LC_X1_Y8_N2 9 " "Info: 2: + IC(5.096 ns) + CELL(0.115 ns) = 6.680 ns; Loc. = LC_X1_Y8_N2; Fanout = 9; REG Node = 'data\[0\]~en'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.211 ns" { BUSY data[0]~en } "NODE_NAME" } } { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 23.71 % ) " "Info: Total cell delay = 1.584 ns ( 23.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.096 ns ( 76.29 % ) " "Info: Total interconnect delay = 5.096 ns ( 76.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.680 ns" { BUSY data[0]~en } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.680 ns" { BUSY BUSY~out0 data[0]~en } { 0.000ns 0.000ns 5.096ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 4.251 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 4.251 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.071 ns) + CELL(0.711 ns) 4.251 ns data\[0\]~en 2 REG LC_X1_Y8_N2 9 " "Info: 2: + IC(2.071 ns) + CELL(0.711 ns) = 4.251 ns; Loc. = LC_X1_Y8_N2; Fanout = 9; REG Node = 'data\[0\]~en'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk data[0]~en } "NODE_NAME" } } { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 51.28 % ) " "Info: Total cell delay = 2.180 ns ( 51.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.071 ns ( 48.72 % ) " "Info: Total interconnect delay = 2.071 ns ( 48.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.251 ns" { clk data[0]~en } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.251 ns" { clk clk~out0 data[0]~en } { 0.000ns 0.000ns 2.071ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.680 ns" { BUSY data[0]~en } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.680 ns" { BUSY BUSY~out0 data[0]~en } { 0.000ns 0.000ns 5.096ns } { 0.000ns 1.469ns 0.115ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.251 ns" { clk data[0]~en } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.251 ns" { clk clk~out0 data[0]~en } { 0.000ns 0.000ns 2.071ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk data\[4\] data\[0\]~en 10.088 ns register " "Info: tco from clock \"clk\" to destination pin \"data\[4\]\" through register \"data\[0\]~en\" is 10.088 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.251 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 4.251 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.071 ns) + CELL(0.711 ns) 4.251 ns data\[0\]~en 2 REG LC_X1_Y8_N2 9 " "Info: 2: + IC(2.071 ns) + CELL(0.711 ns) = 4.251 ns; Loc. = LC_X1_Y8_N2; Fanout = 9; REG Node = 'data\[0\]~en'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk data[0]~en } "NODE_NAME" } } { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 51.28 % ) " "Info: Total cell delay = 2.180 ns ( 51.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.071 ns ( 48.72 % ) " "Info: Total interconnect delay = 2.071 ns ( 48.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.251 ns" { clk data[0]~en } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.251 ns" { clk clk~out0 data[0]~en } { 0.000ns 0.000ns 2.071ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.613 ns + Longest register pin " "Info: + Longest register to pin delay is 5.613 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data\[0\]~en 1 REG LC_X1_Y8_N2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y8_N2; Fanout = 9; REG Node = 'data\[0\]~en'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data[0]~en } "NODE_NAME" } } { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.539 ns) + CELL(2.074 ns) 5.613 ns data\[4\] 2 PIN PIN_6 0 " "Info: 2: + IC(3.539 ns) + CELL(2.074 ns) = 5.613 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'data\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.613 ns" { data[0]~en data[4] } "NODE_NAME" } } { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.074 ns ( 36.95 % ) " "Info: Total cell delay = 2.074 ns ( 36.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.539 ns ( 63.05 % ) " "Info: Total interconnect delay = 3.539 ns ( 63.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.613 ns" { data[0]~en data[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.613 ns" { data[0]~en data[4] } { 0.000ns 3.539ns } { 0.000ns 2.074ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.251 ns" { clk data[0]~en } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.251 ns" { clk clk~out0 data[0]~en } { 0.000ns 0.000ns 2.071ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.613 ns" { data[0]~en data[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.613 ns" { data[0]~en data[4] } { 0.000ns 3.539ns } { 0.000ns 2.074ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "data\[0\]~en BUSY clk -2.414 ns register " "Info: th for register \"data\[0\]~en\" (data pin = \"BUSY\", clock pin = \"clk\") is -2.414 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 4.251 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 4.251 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.071 ns) + CELL(0.711 ns) 4.251 ns data\[0\]~en 2 REG LC_X1_Y8_N2 9 " "Info: 2: + IC(2.071 ns) + CELL(0.711 ns) = 4.251 ns; Loc. = LC_X1_Y8_N2; Fanout = 9; REG Node = 'data\[0\]~en'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk data[0]~en } "NODE_NAME" } } { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 51.28 % ) " "Info: Total cell delay = 2.180 ns ( 51.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.071 ns ( 48.72 % ) " "Info: Total interconnect delay = 2.071 ns ( 48.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.251 ns" { clk data[0]~en } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.251 ns" { clk clk~out0 data[0]~en } { 0.000ns 0.000ns 2.071ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.680 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.680 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns BUSY 1 PIN PIN_45 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_45; Fanout = 1; PIN Node = 'BUSY'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { BUSY } "NODE_NAME" } } { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.096 ns) + CELL(0.115 ns) 6.680 ns data\[0\]~en 2 REG LC_X1_Y8_N2 9 " "Info: 2: + IC(5.096 ns) + CELL(0.115 ns) = 6.680 ns; Loc. = LC_X1_Y8_N2; Fanout = 9; REG Node = 'data\[0\]~en'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.211 ns" { BUSY data[0]~en } "NODE_NAME" } } { "lcd1.vhd" "" { Text "F:/BOOKS/胜达资料/EDA实验（SOPC）/SOPC/EDAV(1C12)/test_51/lcd1/lcd1.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 23.71 % ) " "Info: Total cell delay = 1.584 ns ( 23.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.096 ns ( 76.29 % ) " "Info: Total interconnect delay = 5.096 ns ( 76.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.680 ns" { BUSY data[0]~en } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.680 ns" { BUSY BUSY~out0 data[0]~en } { 0.000ns 0.000ns 5.096ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.251 ns" { clk data[0]~en } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.251 ns" { clk clk~out0 data[0]~en } { 0.000ns 0.000ns 2.071ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.680 ns" { BUSY data[0]~en } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.680 ns" { BUSY BUSY~out0 data[0]~en } { 0.000ns 0.000ns 5.096ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 24 22:27:48 2008 " "Info: Processing ended: Sat May 24 22:27:48 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}