lcd1.vhd

通过VHDL写的128*32液晶驱动接口。

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.all;
USE work.rom.all;
ENTITY lcd1 is
   PORT(--addr: IN std_logic_vector(7 DOWNTO 0);
        clk ,BUSY: IN std_logic;
        STOBE : OUT std_logic;
        data: OUT std_logic_vector(7 DOWNTO 0));
END lcd1;
ARCHITECTURE beha OF lcd1 IS
signal st: std_logic;
BEGIN
stobe<=st;
output:PROCESS(clk)
	variable addr : std_logic_vector(7 DOWNTO 0);
   BEGIN
    if clk'event AND clk='1' then 
		addr := "00000011";
		if BUSY ='1' then
         data <= rom (CONV_INTEGER (addr));
         ST <= '1';
      	ELSE
         data <= (OTHERS =>'Z');
		 ST<='0';
	end if;
	end if;
   END PROCESS;
END beha;