urisc.vhd

用代码来控制urisc控制器

library ieee;
use IEEE.Std_logic_1164.all;
use IEEE.Std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity urisc is 
     PORT(READ_FROM_RAM:in std_logic_vector(7 downto 0);
        WRITE_TO_RAM:out std_logic_vector(7 downto 0);
        ADDRESS:out std_logic_vector(7 downto 0);
        WRITE:out std_logic;
        READ:out std_logic;
        run,clk:in std_logic);
   end urisc;

architecture behavior of urisc is
    signal BUS_A,R,R_NOT,BUS_B,MDR1,MDR:std_logic_vector(7 downto 0);
    
    --signal PC:std_logic_vector(7 downto 0):="00000001";
    signal PC1:std_logic_vector(7 downto 0):="00000001";
    signal PC:std_logic_vector(7 downto 0):="00000001";
    signal PH1,PH2,R_IN,MDR_IN,N_IN,C_IN,MAR_IN:std_logic;
    signal COMP,MDR_OUT,PC_IN,PC_OUT,Z_IN,k,CLEAR:std_logic;
    signal CARRY:std_logic:='0';
    signal C:std_logic_vector(3 downto 0):="0000";
   -- variable K:integer range 0 to 1:=1;	

       begin
    ------------------program counter------------------------------
       pc_reg:process(PC_IN,PH2)
         begin 
           if PC_IN='1' and PH2='0' and PH2'event then
           PC<=BUS_B ;
           else
           PC1<=PC;
                      
           end if;
         end process pc_reg;
    ---------------------register R-------------------------------
       r_reg:block(R_IN='1' and MDR_OUT='1' and PH2='0' and PH2'event)
       begin
           R<= guarded MDR ;
           R_NOT<= not R ;
           end block r_reg;
   -------------------------adder---------------------------------
      process(BUS_A,R_NOT,C_IN,COMP) 
           begin 
        case COMP is
           when '0' => BUS_B<=BUS_A+("0000000"&C_IN);
           when '1' => BUS_B<=BUS_A+R_NOT+("0000000"&C_IN);   
           when others =>null;
        end case;  
        end PROCESS;

   ----------------------register N--------------------------------
     -- n_reg:block(N_IN='1' and PH2='0' and PH2'event)
     -- begin 
      --    N<=guarded N_OUT  else
      --       'Z' ;
    --  end block n_reg;
   --   n_reg:process(N_IN,PH2)
    --   begin
     --    if N_IN='1' and PH2='0' and PH2'event then
    --         N<=N_OUT;
      --   else N<='Z';
     --     end if;
   --    end process;
   ----------------------register Z--------------------------------
     -- z_reg:block(Z_IN='1' and PH2='0' and PH2'event)
     -- begin
      --   Z<=guarded Z_OUT  else
      --      'Z' ;
     -- end block z_reg;
   --   z_reg:process(Z_IN,PH2)
    --   begin
     --    if Z_IN='1' and PH2='0' and PH2'event then
     --        Z<=Z_OUT;
    --     else Z<='Z';
    --      end if;
     --  end process;
   -------------------data register MDR----------------------------
      mdr_reg:process(MDR_IN,PH2)
      begin
      if MDR_IN='1' and PH2='0' and PH2'event then
      WRITE_TO_RAM<= BUS_B  ;
      else null;
      end if;
      end process;
     process(MAR_IN,READ_FROM_RAM)
      begin 
       if MAR_IN ='1' then
       MDR<=READ_FROM_RAM;
        else null;
      end if;
      end process;
 -------------------------------------------------------------------
     BUSA:process(MDR_OUT,MDR,PC1)
        begin
          if MDR_OUT='1' then
           BUS_A<=MDR; 
          else  
           BUS_A<=PC1;
         end if;
        end process;
   ----------------address register MAR----------------------------
     mar_reg:process(MAR_IN,BUS_B,PH2)
         begin
          if MAR_IN='1' and PH2='0' and PH2'event then
          ADDRESS<=BUS_B;
          else null;
         end if;
     end process;
   -------------inside double phrase clock-------------------------
     dpclk:process(clk,run)
        begin
          if run='1' then
          k<='0';
         elsif clk='1' and clk'event then 
           case k is
             when '0' => PH1<='0';PH2<='1';k<='1';
             when '1' => PH1<='1';PH2<='0';k<='0';
             when others=> null;
           end case;
         else null;
        end if;
     end process;
         ----------------counter C----------------------------------
      counter:process(PH1,run)
      begin
       if PH1='0' and PH1'EVENT and CLEAR='0' then
          C<=C+"0001";
       elsif CLEAR='1' and PH1='0' then
          C<="0001";
       else null;
       end if;
       end process;
    ---------------------ROM-----------------------------------
     ROM:process(C)
     type SQ_ARRAY is array(0 to 9,0 to 12) of std_logic;
     constant MEM:SQ_ARRAY:=
    ---PCOUT---ZIN---MARIN---READ---ZEND---MDROUT---RIN---CIN---PCIN---COMP---NIN---MDRIN---CLEAR-------
    (('0',     '0',    '0',    '0',    '0',    '1',   '0',  '0',   '1',     '0',  '0',   '0',    '0'),
     (  '1',   '1'  , '1',   '1',    '1',    '0',   '0',  '0',  '0',   '0',   '0',   '0',    '0'),
      ( '0',   '0',   '1',   '1',    '0',    '1',   '0',  '0',  '0',   '0',   '0',    '0',    '0'),
      ('0',     '0',   '0',   '0',    '0',    '1',   '1', '0' ,  '0' ,  '0',   '0',    '0' ,   '0'),
      ('1',     '0',   '1',   '1',    '0',    '0',   '0',  '1',   '1',   '0',   '0',   '0',     '0'),
      ('0',     '0',    '1',   '1',   '0',     '1',   '0', '0',    '0',  '0',    '0',   '0',     '0'),
      ('0',     '0',    '0',   '0',    '0',    '1',   '0',  '1',   '0' ,  '1',  '1',    '1',      '0'),
      ('1',     '0',     '1',  '1',    '0',    '0',    '0',  '1',   '1',   '0',  '0',    '0',     '0'),
      ('1',     '0',    '0',    '0',   '0',    '0',    '0',  '1',   '1',    '0',  '0',    '0',    '0'),
      ('0',     '0',    '0',    '0',    '0',    '1',   '0',  '0',   '1',     '0',  '0',   '0',    '1'));
     begin
       PC_OUT<=MEM(conv_integer(C),0) ;
       Z_IN <=MEM(conv_integer(C),1);
       MAR_IN<=MEM(conv_integer(C),2) ;
       READ<=MEM(conv_integer(C),3) ;
     --  ZEND<=MEM(conv_integer(C),4);
       MDR_OUT<=MEM(conv_integer(C),5);
       R_IN<=MEM(conv_integer(C),6);
       C_IN<=MEM(conv_integer(C),7) ;
       PC_IN<=MEM(conv_integer(C),8) ;
       COMP<=MEM(conv_integer(C),9) ;
      N_IN  <=MEM(conv_integer(C),10) ;
      MDR_IN<=MEM(conv_integer(C),11) ;
      CLEAR<=MEM(conv_integer(C),12) ;
      WRITE<=COMP;
     end process;

    end behavior;