ram.vhd

来自「用代码来控制urisc控制器」· VHDL 代码 · 共 32 行

library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity ram is
   port( RAM_IN:in std_logic_vector(7 downto 0);
         RAM_OUT:out std_logic_vector(7 downto 0);
         WRITER,READR:in std_logic;
         ADDRESS_RAM:in std_logic_vector(7 downto 0)
         );
   end ram;
architecture behave of ram is
   type memory is array(0 to 15) of std_logic_vector(3 downto 0);
   --function INTVAL(VAL:in std_logic_vector) return integer;
   signal mem:memory:=(("0001"),("0011"),("0101"),("0111"),
                       ("0001"),("1001"),("0010"),("0010"),
                       ("0001"),("0001"),("0010"),("0010"),
                       ("0001"),("0001"),("0010"),("0010"));
   begin
         access_ram:process(RAM_IN,WRITER,READR,ADDRESS_RAM)
         begin
           if READR='1' then 
             RAM_OUT<="0000"&mem(conv_integer(ADDRESS_RAM(3 downto 0)));
           elsif WRITER='1' then
             mem(conv_integer(ADDRESS_RAM(3 downto 0)))<=RAM_IN(3 downto 0);
           else null;
           end if;
         end process;
   end behave;