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}
Block {
BlockType Reference
Name "out_sop"
Ports [1, 1]
Position [535, 597, 600, 613]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder2/AltBus"
SourceType "AltBus AlteraBlockset"
BusType "Single Bit"
bwl "8"
bwr "0"
saturate off
}
Block {
BlockType Reference
Name "out_valid"
Ports [1, 1]
Position [550, 522, 615, 538]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder2/AltBus"
SourceType "AltBus AlteraBlockset"
BusType "Single Bit"
bwl "8"
bwr "0"
saturate off
}
Block {
BlockType Outport
Name "In_ready"
Position [650, 483, 680, 497]
ForegroundColor "blue"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "Out_valid"
Position [640, 523, 670, 537]
ForegroundColor "blue"
Port "2"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "Out_data[15:0]"
Position [630, 413, 660, 427]
ForegroundColor "blue"
Port "3"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "Out_sop"
Position [625, 598, 655, 612]
ForegroundColor "blue"
Port "4"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "Out_eop"
Position [610, 673, 640, 687]
ForegroundColor "blue"
Port "5"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "In_data[34:0]"
SrcPort 1
Points [0, 0]
DstBlock "in_data"
DstPort 1
}
Line {
SrcBlock "Out_ready"
SrcPort 1
DstBlock "out_ready"
DstPort 1
}
Line {
SrcBlock "In_valid"
SrcPort 1
Points [0, 0]
DstBlock "in_valid"
DstPort 1
}
Line {
SrcBlock "In_sop"
SrcPort 1
Points [0, 0]
DstBlock "in_sop"
DstPort 1
}
Line {
SrcBlock "In_eop"
SrcPort 1
DstBlock "in_eop"
DstPort 1
}
Line {
SrcBlock "in_ready"
SrcPort 1
Points [0, 0]
DstBlock "In_ready"
DstPort 1
}
Line {
SrcBlock "out_valid"
SrcPort 1
Points [0, 0]
DstBlock "Out_valid"
DstPort 1
}
Line {
SrcBlock "out_sop"
SrcPort 1
Points [0, 0]
DstBlock "Out_sop"
DstPort 1
}
Line {
SrcBlock "out_eop"
SrcPort 1
Points [0, 0]
DstBlock "Out_eop"
DstPort 1
}
Line {
SrcBlock "in_data"
SrcPort 1
DstBlock "Saturate"
DstPort 1
}
Line {
SrcBlock "out_data"
SrcPort 1
Points [0, 0]
DstBlock "Out_data[15:0]"
DstPort 1
}
Line {
SrcBlock "Saturate"
SrcPort 1
DstBlock "Round"
DstPort 1
}
Line {
SrcBlock "Round"
SrcPort 1
Points [0, 0]
DstBlock "out_data"
DstPort 1
}
Line {
SrcBlock "out_ready"
SrcPort 1
DstBlock "in_ready"
DstPort 1
}
Line {
SrcBlock "in_sop"
SrcPort 1
Points [0, 0]
DstBlock "out_sop"
DstPort 1
}
Line {
SrcBlock "in_eop"
SrcPort 1
Points [0, 0]
DstBlock "out_eop"
DstPort 1
}
Line {
SrcBlock "in_valid"
SrcPort 1
Points [0, 0]
DstBlock "out_valid"
DstPort 1
}
}
}
Block {
BlockType Reference
Name "SignalCompiler"
Ports []
Position [1059, 58, 1128, 105]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder2/Signal Compiler"
SourceType "Signal Compiler AlteraBlockset"
DeviceFamily "Stratix II"
DeviceName "AUTO"
EnableSignalTap off
SignalTapDepth "128"
UseBoardBlock off
StpUseDefaultClock on
StpClock "Clock"
}
Block {
BlockType Step
Name "Step"
Position [45, 335, 75, 365]
Time "5*clock1"
SampleTime "clock1"
ZeroCross off
}
Block {
BlockType Terminator
Name "Terminator"
Position [675, 250, 695, 270]
}
Block {
BlockType Terminator
Name "Terminator1"
Position [1000, 340, 1020, 360]
}
Block {
BlockType Terminator
Name "Terminator2"
Position [1000, 475, 1020, 495]
}
Block {
BlockType Reference
Name "VCC"
Ports [0, 1]
Position [1220, 297, 1235, 313]
ForegroundColor "darkGreen"
SourceBlock "allblocks_alteradspbuilder2/VCC"
SourceType "VCC AlteraBlockset"
SpecifyClock off
}
Block {
BlockType Reference
Name "cic"
Ports [8, 7]
Position [465, 196, 650, 499]
ForegroundColor "orange"
DropShadow on
SourceBlock "megacorefunctions_alteradspbuilder2/MegaCore"
SourceType "fft"
entityName "cic_import"
inNames "clken in_data in_endofpacket in_error in_starto"
"fpacket in_valid out_ready reset_n "
inBwls "1 8 1 2 1 1 1 1"
inBwrs "0 0 0 0 0 0 0 0"
inTypes "b u b u b b b b "
inDelayed "1 1 1 1 1 1 1 0"
outNames "in_ready out_channel out_data out_endofpacket o"
"ut_error out_startofpacket out_valid "
outBwls "1 1 16 1 2 1 1"
outBwrs "0 0 0 0 0 0 0"
outTypes "b b u b u b b "
xmlmapfile "c:\\altera\\71sp1\\quartus\\dsp_builder\\lib\\S"
"imgenCMap.xml"
launch_params "-parameterization.megawizard2:1 -hide_splash -"
"parameterization.activate_atstartup:1 -hide_iptb -parameterization.window_loc"
"ation:center -limitfiles"
is_megacore "on"
use_dynamic_feedthrough_data "on"
vofile "DSPBuilder_TDMDDC_import\\cic.vo"
n_input_port "8"
n_output_port "7"
core_dir "C:\\altera\\71sp1\\ip\\cic\\lib\\ip_toolbench"
core_name "cic"
clockname "clk"
flow_dir "C:\\altera\\71sp1\\ip\\cic\\lib\\../../common/i"
"p_toolbench/v1.3.0/bin"
core_version "7.1"
NewVariation "off"
VhdlVariationDate "06-Jul-2007 14:53:41"
VhdlVariationName "C:\\DesignExample\\tdmddc_v71\\DSPBuilder_TDMDD"
"C_import\\cic.vhd"
use_systemC_model "off"
wizard "cic"
inptype "bububbbb"
outptype "bbububb"
Port {
PortNumber 1
Name "inready"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 2
Name "outchan"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 3
Name "dout"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 4
Name "ciceop"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 5
Name "outerr"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 6
Name "cicsop"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 7
Name "outvalid"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Reference
Name "cic_clken"
Ports [1, 1]
Position [350, 217, 415, 233]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder2/Input"
SourceType "Input AlteraBlockset"
iofile "C:\\DesignExample\\tdmddc_v71\\tb_TDMDDC\\TDMDD"
"C_cic_clken.salt"
BusType "Single Bit"
bwl "8"
bwr "0"
SpecifyClock off
PORTTYPE "Input"
}
Block {
BlockType Reference
Name "cic_din"
Ports [1, 1]
Position [350, 252, 415, 268]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder2/Input"
SourceType "Input AlteraBlockset"
iofile "C:\\DesignExample\\tdmddc_v71\\tb_TDMDDC\\TDMDD"
"C_cic_din.salt"
BusType "Signed Integer"
bwl "8"
bwr "0"
SpecifyClock off
PORTTYPE "Input"
}
Block {
BlockType Reference
Name "cic_ieop"
Ports [1, 1]
Position [350, 287, 415, 303]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder2/Input"
SourceType "Input AlteraBlockset"
iofile "C:\\DesignExample\\tdmddc_v71\\tb_TDMDDC\\TDMDD"
"C_cic_ieop.salt"
BusType "Single Bit"
bwl "8"
bwr "0"
SpecifyClock off
PORTTYPE "Input"
}
Block {
BlockType Reference
Name "cic_ierr"
Ports [1, 1]
Position [345, 322, 410, 338]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder2/Input"
SourceType "Input AlteraBlockset"
iofile "C:\\DesignExample\\tdmddc_v71\\tb_TDMDDC\\TDMDD"
"C_cic_ierr.salt"
BusType "Single Bit"
bwl "8"
bwr "0"
SpecifyClock off
PORTTYPE "Input"
}
Block {
BlockType Reference
Name "cic_isop"
Ports [1, 1]
Position [345, 357, 410, 373]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder2/Input"
SourceType "Input AlteraBlockset"
iofile "C:\\DesignExample\\tdmddc_v71\\tb_TDMDDC\\TDMDD"
"C_cic_isop.salt"
BusType "Single Bit"
bwl "8"
bwr "0"
SpecifyClock off
PORTTYPE "Input"
}
Block {
BlockType Reference
Name "cic_ival"
Ports [1, 1]
Position [345, 392, 410, 408]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder2/Input"
SourceType "Input AlteraBlockset"
iofile "C:\\DesignExample\\tdmddc_v71\\tb_TDMDDC\\TDMDD"
"C_cic_ival.salt"
BusType "Single Bit"
bwl "8"
bwr "0"
SpecifyClock off
PORTTYPE "Input"
}
Block {
BlockType Reference
Name "cic_rstn"
Ports [1, 1]
Position [105, 462, 170, 478]
ForegroundColor "red"
SourceBlock "allblocks_alteradspbuilder2/Input"
SourceType "Input AlteraBlockset"
iofile "C:\\DesignExample\\tdmddc_v71\\tb_TDMDDC\\TDMDD"
"C_cic_rstn.salt"
BusType "Single Bit"
bwl "8"
bwr "0"
SpecifyClock off
PORTTYPE "Input"
}
Block {
BlockType SubSystem
Name "data source"
Ports [2, 4]
Position [120, 237, 210, 388]
TreatAsAtomicUnit on
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
Port {
PortNumber 4
Name "invalid"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
System {
Name "data source"
Location [0, 84, 1140, 837]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
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