📄 fir.vhd
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-- megafunction wizard: %FIR Compiler v7.1%
-- GENERATION: XML
-- ============================================================
-- Megafunction Name(s):
-- fir_ast
-- ============================================================
-- Generated by FIR Compiler 7.1 [Altera, IP Toolbench 1.3.0 Build 177]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2007 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY fir IS
PORT (
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
ast_sink_data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
ast_sink_valid : IN STD_LOGIC;
ast_source_ready : IN STD_LOGIC;
ast_sink_sop : IN STD_LOGIC;
ast_sink_eop : IN STD_LOGIC;
ast_sink_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ast_source_data : OUT STD_LOGIC_VECTOR (34 DOWNTO 0);
ast_sink_ready : OUT STD_LOGIC;
ast_source_valid : OUT STD_LOGIC;
ast_source_sop : OUT STD_LOGIC;
ast_source_eop : OUT STD_LOGIC;
ast_source_channel : OUT STD_LOGIC;
ast_source_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END fir;
ARCHITECTURE SYN OF fir IS
attribute altera_attribute : string;
attribute altera_attribute of SYN: ARCHITECTURE is "suppress_da_rule_internal=z100";
COMPONENT fir_ast
PORT (
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
ast_sink_data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
ast_sink_valid : IN STD_LOGIC;
ast_source_ready : IN STD_LOGIC;
ast_sink_sop : IN STD_LOGIC;
ast_sink_eop : IN STD_LOGIC;
ast_sink_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ast_source_data : OUT STD_LOGIC_VECTOR (34 DOWNTO 0);
ast_sink_ready : OUT STD_LOGIC;
ast_source_valid : OUT STD_LOGIC;
ast_source_sop : OUT STD_LOGIC;
ast_source_eop : OUT STD_LOGIC;
ast_source_channel : OUT STD_LOGIC;
ast_source_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
fir_ast_inst : fir_ast
PORT MAP (
clk => clk,
reset_n => reset_n,
ast_sink_data => ast_sink_data,
ast_source_data => ast_source_data,
ast_sink_valid => ast_sink_valid,
ast_sink_ready => ast_sink_ready,
ast_source_valid => ast_source_valid,
ast_source_ready => ast_source_ready,
ast_sink_sop => ast_sink_sop,
ast_sink_eop => ast_sink_eop,
ast_source_sop => ast_source_sop,
ast_source_eop => ast_source_eop,
ast_source_channel => ast_source_channel,
ast_sink_error => ast_sink_error,
ast_source_error => ast_source_error
);
END SYN;
-- =========================================================
-- FIR Compiler Wizard Data
-- ===============================
-- DO NOT EDIT FOLLOWING DATA
-- @Altera, IP Toolbench@
-- Warning: If you modify this section, FIR Compiler Wizard may not be able to reproduce your chosen configuration.
--
-- Retrieval info: <?xml version="1.0"?>
-- Retrieval info: <MEGACORE title="FIR Compiler" version="7.1" build="177" iptb_version="1.3.0 Build 177" format_version="120" >
-- Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.FIRModelClass" active_core="fir_ast" >
-- Retrieval info: <STATIC_SECTION>
-- Retrieval info: <PRIVATES>
-- Retrieval info: <NAMESPACE name = "parameterization">
-- Retrieval info: <PRIVATE name = "use_mem" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_type" value="M512" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "filter_rate" value="Decimation" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "filter_factor" value="2" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "coefficient_scaling_type" value="None" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "coefficient_scaling_factor" value="1.0" type="STRING" enable="0" />
-- Retrieval info: <PRIVATE name = "coefficient_bit_width" value="18" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "coefficient_binary_point_position" value="0" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "number_of_input_channels" value="2" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "input_number_system" value="Signed Binary" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "input_bit_width" value="16" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "input_binary_point_position" value="0" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "output_bit_width_method" value="Actual Coefficients" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "output_number_system" value="Full Resolution" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "output_bit_width" value="35" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "output_bits_right_of_binary_point" value="32" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "output_bits_removed_from_lsb" value="0" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "output_lsb_remove_type" value="Truncate" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "output_msb_remove_type" value="Truncate" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "flow_control" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "flow_control_input" value="Slave Sink" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "flow_control_output" value="Master Source" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "device_family" value="Stratix II" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "structure" value="Variable/Fixed Coefficient : Multi-Cycle" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "pipeline_level" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "clocks_to_compute" value="4" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "number_of_serial_units" value="2" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "data_storage" value="Auto" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "coefficient_storage" value="M4K" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "multiplier_storage" value="DSP Blocks" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "force_non_symmetric_structure" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "coefficients_reload" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "coefficients_reload_sgl_clock" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "max_clocks_to_compute" value="4" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "set_1" value="Low Pass Set, Imported, C:\MyDesigns\TDMDDC71\fdcoeffR4N8M1L110.txt, -99.0, 67.0, 139.0, -4.0, -163.0, -82.0, 153.0, 182.0, -93.0, -278.0, -34.0, 331.0, 221.0, -297.0, -436.0, 135.0, 613.0, 160.0, -670.0, -553.0, 522.0, 946.0, -132.0, -1210.0, -481.0, 1194.0, 1200.0, -790.0, -1839.0, -31.0, 2156.0, 1165.0, -1932.0, -2387.0, 1022.0, 3348.0, 553.0, -3663.0, -2590.0, 2973.0, 4662.0, -1071.0, -6188.0, -2047.0, 6450.0, 6079.0, -4706.0, -10437.0, 85.0, 14081.0, 8654.0, -15039.0, -24714.0, 5853.0, 58843.0, 85316.0, 58843.0, 5853.0, -24714.0, -15039.0, 8654.0, 14081.0, 85.0, -10437.0, -4706.0, 6079.0, 6450.0, -2047.0, -6188.0, -1071.0, 4662.0, 2973.0, -2590.0, -3663.0, 553.0, 3348.0, 1022.0, -2387.0, -1932.0, 1165.0, 2156.0, -31.0, -1839.0, -790.0, 1200.0, 1194.0, -481.0, -1210.0, -132.0, 946.0, 522.0, -553.0, -670.0, 160.0, 613.0, 135.0, -436.0, -297.0, 221.0, 331.0, -34.0, -278.0, -93.0, 182.0, 153.0, -82.0, -163.0, -4.0, 139.0, 67.0, -99.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "number_of_sets" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "output_full_bit_width" value="35" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "output_full_bits_right_of_binary_point" value="32" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "coefficient_reload_bit_width" value="18" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "logic_cell" value="641" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "m512" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "m4k" value="11" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "m144k" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "m9k" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "mlab" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "megaram" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "dsp_block" value="14" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "input_clock_period" value="4" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "output_clock_period" value="8" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "throughput" value="8" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "memory_units" value="4" type="INTEGER" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "simgen_enable">
-- Retrieval info: <PRIVATE name = "matlab_enable" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "testbench_enable" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "testbench_simulation_clock_period" value="10.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "language" value="VHDL" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "enabled" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "simgen">
-- Retrieval info: <PRIVATE name = "parameter" value="SIMGEN_OPTIMIZATION=ALL" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "filename" value="fir.vho" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "serializer"/>
-- Retrieval info: </PRIVATES>
-- Retrieval info: <FILES/>
-- Retrieval info: <PORTS/>
-- Retrieval info: <LIBRARIES/>
-- Retrieval info: </STATIC_SECTION>
-- Retrieval info: </NETLIST_SECTION>
-- Retrieval info: </MEGACORE>
-- =========================================================
-- RELATED_FILES: fir_st.v, fir_constraints.tcl, fir_ast.vhd, fir.vhd, fir_ast.vhd, fir_st.v, fir.vhd;
-- IPFS_FILES: fir.vho;
-- =========================================================
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