alt_avalonst_pfc_0.v

ddc的vhdl源代码

// --------------------------------------------------------------------------------
//| Packet Format Converter
// --------------------------------------------------------------------------------
// Packet Descriptors
// in0 : I,Q / 1
// out0 : I / 1
// out1 : Q / 1

`timescale 100ps / 100ps
module alt_avalonst_pfc_0 (
    
      // Interface: clk
      input              clk,
      input              reset_n,
      // Interface: in0
      input              in0_valid,
      output reg         in0_ready,
      input      [15: 0] in0_data,
      input              in0_startofpacket,
      input              in0_endofpacket,
      // Interface: out0
      output reg         out0_valid,
      input              out0_ready,
      output reg [15: 0] out0_data,
      output reg         out0_startofpacket,
      output reg         out0_endofpacket,
      output reg [ 0: 0] out0_error,
      // Interface: out1
      output reg         out1_valid,
      input              out1_ready,
      output reg [15: 0] out1_data,
      output reg         out1_startofpacket,
      output reg         out1_endofpacket,
      output reg [ 0: 0] out1_error
);


   // ---------------------------------------------------------------------
   //| Signal Declarations
   // ---------------------------------------------------------------------
   
   // ------------------
   // Errdor Handling
   reg          error_reset_n;
   reg          error_detected;
   reg          internal_reset_n;


   // ------------------
   // Input Control
   reg  [ 3: 0] in0_wr_ptr;
   reg  [ 3: 0] in0_beat_counter;
   reg  [15: 0] in0_mem [15:0];
   reg  [ 6: 0] in0_space_used;
   reg  [ 6: 0] in0_new_beats_available;   
   reg  [ 6: 0] in0_beats_available;
   reg          in0_waiting_for_sop;
   reg  [ 6: 0] in0_beats_available_minus_enable;
      

   // ------------------
   // p2 stage
   reg          p2_beat_counter;
   reg          p2_data_available;
   reg          p2_enable;
   reg  [ 6: 0] p2_out0_beats_used; // Warning: Stale value
   reg  [ 6: 0] p2_out0_new_beats_used; // Warning: Stale value
   reg          p2_out0_valid;         
   reg          p2_out0_startofpacket; 
   reg          p2_out0_endofpacket;   
   reg          p2_out0_empty;

   reg  [ 9: 0] p2_out0_s0_select;   // The input symbol to take from
   reg  [ 3: 0] p2_out0_s0_in0_rd_ptr;
   reg  [ 6: 0] p2_out0_in0_space_available;
   reg  [ 6: 0] p2_out1_beats_used; // Warning: Stale value
   reg  [ 6: 0] p2_out1_new_beats_used; // Warning: Stale value
   reg          p2_out1_valid;         
   reg          p2_out1_startofpacket; 
   reg          p2_out1_endofpacket;   
   reg          p2_out1_empty;

   reg  [ 9: 0] p2_out1_s0_select;   // The input symbol to take from
   reg  [ 3: 0] p2_out1_s0_in0_rd_ptr;
   reg  [ 6: 0] p2_out1_in0_space_available;

   // ------------------
   // p1 stage
   reg          p1_enable;
   reg          p1_out0_valid; 
   reg          p1_out0_startofpacket;
   reg          p1_out0_endofpacket;
   reg          p1_out0_empty;
   reg  [ 9: 0] p1_out0_s0_select;
   reg  [ 6: 0] p1_out0_in0_space_available;
   reg  [ 6: 0] p1_out0_in0_space_difference;
   reg          p1_out1_valid; 
   reg          p1_out1_startofpacket;
   reg          p1_out1_endofpacket;
   reg          p1_out1_empty;
   reg  [ 9: 0] p1_out1_s0_select;
   reg  [ 6: 0] p1_out1_in0_space_available;
   reg  [ 6: 0] p1_out1_in0_space_difference;

   // ------------------
   // p0 stage
   reg          p0_enable;
   reg          p0_out0_valid; 
   reg          p0_out0_startofpacket;
   reg          p0_out0_endofpacket;
   reg          p0_out0_empty;

   reg  [ 9: 0] p0_out0_s0_select;
   wire [15: 0] p0_out0_s0_in0_rd_data;
   reg  [ 6: 0] p0_out0_in0_space_difference;
   reg          p0_out1_valid; 
   reg          p0_out1_startofpacket;
   reg          p0_out1_endofpacket;
   reg          p0_out1_empty;

   reg  [ 9: 0] p0_out1_s0_select;
   wire [15: 0] p0_out1_s0_in0_rd_data;
   reg  [ 6: 0] p0_out1_in0_space_difference;

   // ------------------
   // to egress fifo
   wire         tofifo_out0_ready;
   reg          tofifo_out0_valid; 
   reg  [15: 0] tofifo_out0_data;
   reg          tofifo_out0_startofpacket;
   reg          tofifo_out0_endofpacket;
   reg          tofifo_out0_empty;
   reg  [ 0: 0] tofifo_out0_error;
   wire         tofifo_out1_ready;
   reg          tofifo_out1_valid; 
   reg  [15: 0] tofifo_out1_data;
   reg          tofifo_out1_startofpacket;
   reg          tofifo_out1_endofpacket;
   reg          tofifo_out1_empty;
   reg  [ 0: 0] tofifo_out1_error;
 
   // ------------------
   // from egress fifo
   reg          fromfifo_out0_ready;
   wire         fromfifo_out0_valid; 
   wire [15: 0] fromfifo_out0_data;
   wire         fromfifo_out0_startofpacket;
   wire         fromfifo_out0_endofpacket;
   wire         fromfifo_out0_empty;
   wire [ 0: 0] fromfifo_out0_error;
   reg          fromfifo_out1_ready;
   wire         fromfifo_out1_valid; 
   wire [15: 0] fromfifo_out1_data;
   wire         fromfifo_out1_startofpacket;
   wire         fromfifo_out1_endofpacket;
   wire         fromfifo_out1_empty;
   wire [ 0: 0] fromfifo_out1_error;
 
   // ------------------
   // output stage
   reg          tofifo_out_ready;
   reg          tofifo_out_enable;
   reg          tofifo_out0_error_reported;
   reg          tofifo_out1_error_reported;

   // ------------------
   // optimizing
   reg          in0_beats_equals_out0_beats;
   reg          in0_beats_equals_out1_beats;

   // ------------------
   // dummy signals.
   reg          out0_empty = 0;
   reg          out1_empty = 0;

   // ----------------------------------------------------------------------
   //| Reset Control
   // ----------------------------------------------------------------------
   always @* begin
      internal_reset_n = reset_n && error_reset_n;
   end
   
   always @ (negedge reset_n, posedge clk) begin
      if (!reset_n) begin
         error_reset_n <= 0;
      end else begin
      error_reset_n <= 0;
      if (!tofifo_out0_error_reported)
         error_reset_n <= 1;
      if (!tofifo_out1_error_reported)
         error_reset_n <= 1;
      end
   end
   
   

   // ----------------------------------------------------------------------
   //| Input Stages - write to FIFOs. (1 FIFO per input interface/symbol.)
   // ----------------------------------------------------------------------
   always @* begin
        in0_new_beats_available = in0_beats_available;
        
        //----------------------------------------
        // Interface: in0
        if (in0_ready && in0_valid && (in0_startofpacket || ~in0_waiting_for_sop )) begin

           // Update the number of symbols that are available for each 
           // output based on knowledge of the packet format.
           case (in0_beat_counter)
              0 : in0_new_beats_available = in0_beats_available  + 0;
              1 : in0_new_beats_available = in0_beats_available  + 1;
              default : in0_new_beats_available = in0_beats_available  + 0;
           endcase
        end
   end 
   
   always @ (negedge internal_reset_n, posedge clk) begin
      if (!internal_reset_n) begin
        error_detected <= 0;
        in0_ready <= 0;
        in0_wr_ptr <= 0;
        in0_beat_counter <= 0;
        in0_space_used <= 0;
        in0_beats_available <= 0;
        in0_waiting_for_sop <= 1;
      end else begin

        
        //----------------------------------------
        // Interface: in0

        // If the write pointer is getting close to 
        // the read pointer, backpressure
        in0_ready <= 1;  
        
        if (p1_out0_in0_space_difference <= 2 )
           in0_ready <= 0; 
        if (p1_out1_in0_space_difference <= 2 )
           in0_ready <= 0; 

        if (in0_ready && in0_valid && in0_startofpacket)
           in0_waiting_for_sop <= 0;
              
        if (in0_ready && in0_valid && (in0_startofpacket || ~in0_waiting_for_sop )) begin
           in0_wr_ptr <= in0_wr_ptr + 1'b1;
           in0_space_used <= in0_space_used + 1'b1;
       	   in0_beat_counter <= in0_beat_counter + 1'b1;

           if (in0_beat_counter == 1) begin
              in0_beat_counter <= 0;
           end

           // Frame Delineation Error Detection
           if ( (in0_beat_counter == 0)  // SOP Expected
              || (in0_beat_counter == 2) 
              || (in0_beat_counter == 0) 
           ) begin 
              if (in0_startofpacket==0) begin
                 error_detected <= 1;
              end
           end else begin
              if (in0_startofpacket==1) begin
                 error_detected <= 1;
              end
           end           
           
           if ( (in0_beat_counter == 1)  // EOP Expected
              || (in0_beat_counter == 3) 
              || (in0_beat_counter == 1) 
           ) begin 
              if (in0_endofpacket==0) begin
                 error_detected <= 1;
              end
           end else begin
              if (in0_endofpacket==1) begin
                 error_detected <= 1;
              end
           end           

           // Update the number of symbols that are available for each 
           // output based on knowledge of the packet format.
           case (in0_beat_counter)
              0 : in0_beats_available <= in0_beats_available  + 0;
              1 : in0_beats_available <= in0_beats_available  + 1;
           endcase	
        end
        in0_beats_available <= in0_new_beats_available;
      end
   end

   // ---------------------------------------------------------------------
   //| Instantiate Memory
   // ---------------------------------------------------------------------
       altsyncram 
         #(
           .operation_mode ("DUAL_PORT"),
           .width_a       (16),
           .widthad_a     (4),
           .numwords_a    (15+1),      
           .width_b       (16),
           .widthad_b     (4),      
           .numwords_b    (15+1),      
           .address_reg_b ("CLOCK0"),
           .outdata_reg_b ("CLOCK0") 
         ) 
         out0_s0_in0_mem
         (
           .clock0        (clk),
           .wren_a        (in0_ready && in0_valid),
           .address_a     (in0_wr_ptr),
           .data_a        (in0_data),
           .address_b     (p2_out0_s0_in0_rd_ptr),
           .q_b           (p0_out0_s0_in0_rd_data)
         );
       
       altsyncram 
         #(
           .operation_mode ("DUAL_PORT"),
           .width_a       (16),
           .widthad_a     (4),
           .numwords_a    (15+1),      
           .width_b       (16),
           .widthad_b     (4),      
           .numwords_b    (15+1),      
           .address_reg_b ("CLOCK0"),
           .outdata_reg_b ("CLOCK0") 
         ) 
         out1_s0_in0_mem
         (
           .clock0        (clk),
           .wren_a        (in0_ready && in0_valid),
           .address_a     (in0_wr_ptr),
           .data_a        (in0_data),
           .address_b     (p2_out1_s0_in0_rd_ptr),
           .q_b           (p0_out1_s0_in0_rd_data)
         );
       


   // ----------------------------------------------------------------------
   //| Backpressure / Flow control
   // ----------------------------------------------------------------------
   
   // ----------------------------------------------------------------------
   //| Main Output Counter
   // ----------------------------------------------------------------------
   always @ (negedge internal_reset_n, posedge clk) begin
      if (!internal_reset_n) begin
        tofifo_out_enable <= 0;
        p0_enable <= 0;
        p1_enable <= 0;
        p2_enable <= 0;
      end else begin
        tofifo_out_enable <= p0_enable;
        p0_enable <= p1_enable;
        p1_enable <= p2_enable;
        p2_enable <= tofifo_out_ready && p2_data_available;