dds_cordic.tan.qmsg

dds频率生成文件

{ "Info" "ITDB_FULL_TCO_RESULT" "sys_clk OUT\[3\] cordic_m1_rot:inst\|x_out\[3\] 9.801 ns register " "Info: tco from clock \"sys_clk\" to destination pin \"OUT\[3\]\" through register \"cordic_m1_rot:inst\|x_out\[3\]\" is 9.801 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clk source 3.144 ns + Longest register " "Info: + Longest clock path from clock \"sys_clk\" to source register is 3.144 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns sys_clk 1 CLK PIN_209 2 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_209; Fanout = 2; CLK Node = 'sys_clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sys_clk } "NODE_NAME" } } { "DDS_CORDIC.bdf" "" { Schematic "C:/Documents and Settings/Administrator.8F9C194BD37D4C4/桌面/CORDIC_DDS_16bit/DDS_CORDIC.bdf" { { 136 32 200 152 "sys_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.407 ns sys_clk~clkctrl 2 COMB CLKCTRL_G10 589 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.407 ns; Loc. = CLKCTRL_G10; Fanout = 589; COMB Node = 'sys_clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.257 ns" { sys_clk sys_clk~clkctrl } "NODE_NAME" } } { "DDS_CORDIC.bdf" "" { Schematic "C:/Documents and Settings/Administrator.8F9C194BD37D4C4/桌面/CORDIC_DDS_16bit/DDS_CORDIC.bdf" { { 136 32 200 152 "sys_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.071 ns) + CELL(0.666 ns) 3.144 ns cordic_m1_rot:inst\|x_out\[3\] 3 REG LCFF_X35_Y11_N11 1 " "Info: 3: + IC(1.071 ns) + CELL(0.666 ns) = 3.144 ns; Loc. = LCFF_X35_Y11_N11; Fanout = 1; REG Node = 'cordic_m1_rot:inst\|x_out\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.737 ns" { sys_clk~clkctrl cordic_m1_rot:inst|x_out[3] } "NODE_NAME" } } { "cordic_m1_rot.vhd" "" { Text "C:/Documents and Settings/Administrator.8F9C194BD37D4C4/桌面/CORDIC_DDS_16bit/cordic_m1_rot.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.816 ns ( 57.76 % ) " "Info: Total cell delay = 1.816 ns ( 57.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.328 ns ( 42.24 % ) " "Info: Total interconnect delay = 1.328 ns ( 42.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.144 ns" { sys_clk sys_clk~clkctrl cordic_m1_rot:inst|x_out[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.144 ns" { sys_clk sys_clk~combout sys_clk~clkctrl cordic_m1_rot:inst|x_out[3] } { 0.000ns 0.000ns 0.257ns 1.071ns } { 0.000ns 1.150ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "cordic_m1_rot.vhd" "" { Text "C:/Documents and Settings/Administrator.8F9C194BD37D4C4/桌面/CORDIC_DDS_16bit/cordic_m1_rot.vhd" 56 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.353 ns + Longest register pin " "Info: + Longest register to pin delay is 6.353 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cordic_m1_rot:inst\|x_out\[3\] 1 REG LCFF_X35_Y11_N11 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X35_Y11_N11; Fanout = 1; REG Node = 'cordic_m1_rot:inst\|x_out\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cordic_m1_rot:inst|x_out[3] } "NODE_NAME" } } { "cordic_m1_rot.vhd" "" { Text "C:/Documents and Settings/Administrator.8F9C194BD37D4C4/桌面/CORDIC_DDS_16bit/cordic_m1_rot.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.067 ns) + CELL(3.286 ns) 6.353 ns OUT\[3\] 2 PIN PIN_90 0 " "Info: 2: + IC(3.067 ns) + CELL(3.286 ns) = 6.353 ns; Loc. = PIN_90; Fanout = 0; PIN Node = 'OUT\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.353 ns" { cordic_m1_rot:inst|x_out[3] OUT[3] } "NODE_NAME" } } { "DDS_CORDIC.bdf" "" { Schematic "C:/Documents and Settings/Administrator.8F9C194BD37D4C4/桌面/CORDIC_DDS_16bit/DDS_CORDIC.bdf" { { 200 920 1096 216 "OUT\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.286 ns ( 51.72 % ) " "Info: Total cell delay = 3.286 ns ( 51.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.067 ns ( 48.28 % ) " "Info: Total interconnect delay = 3.067 ns ( 48.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.353 ns" { cordic_m1_rot:inst|x_out[3] OUT[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.353 ns" { cordic_m1_rot:inst|x_out[3] OUT[3] } { 0.000ns 3.067ns } { 0.000ns 3.286ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.144 ns" { sys_clk sys_clk~clkctrl cordic_m1_rot:inst|x_out[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.144 ns" { sys_clk sys_clk~combout sys_clk~clkctrl cordic_m1_rot:inst|x_out[3] } { 0.000ns 0.000ns 0.257ns 1.071ns } { 0.000ns 1.150ns 0.000ns 0.666ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.353 ns" { cordic_m1_rot:inst|x_out[3] OUT[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.353 ns" { cordic_m1_rot:inst|x_out[3] OUT[3] } { 0.000ns 3.067ns } { 0.000ns 3.286ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "sys_clk daclk 7.163 ns Longest " "Info: Longest tpd from source pin \"sys_clk\" to destination pin \"daclk\" is 7.163 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns sys_clk 1 CLK PIN_209 2 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_209; Fanout = 2; CLK Node = 'sys_clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sys_clk } "NODE_NAME" } } { "DDS_CORDIC.bdf" "" { Schematic "C:/Documents and Settings/Administrator.8F9C194BD37D4C4/桌面/CORDIC_DDS_16bit/DDS_CORDIC.bdf" { { 136 32 200 152 "sys_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.677 ns) + CELL(3.336 ns) 7.163 ns daclk 2 PIN PIN_118 0 " "Info: 2: + IC(2.677 ns) + CELL(3.336 ns) = 7.163 ns; Loc. = PIN_118; Fanout = 0; PIN Node = 'daclk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.013 ns" { sys_clk daclk } "NODE_NAME" } } { "DDS_CORDIC.bdf" "" { Schematic "C:/Documents and Settings/Administrator.8F9C194BD37D4C4/桌面/CORDIC_DDS_16bit/DDS_CORDIC.bdf" { { 144 920 1096 160 "daclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.486 ns ( 62.63 % ) " "Info: Total cell delay = 4.486 ns ( 62.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.677 ns ( 37.37 % ) " "Info: Total interconnect delay = 2.677 ns ( 37.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.163 ns" { sys_clk daclk } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.163 ns" { sys_clk sys_clk~combout daclk } { 0.000ns 0.000ns 2.677ns } { 0.000ns 1.150ns 3.336ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 05 22:24:09 2007 " "Info: Processing ended: Wed Dec 05 22:24:09 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}