fft_small_tb.vhd

FFT 32k use VHDL MATLAB

        if(reset='1' or master_sink_ena_reg='0') then                                                                         
          counter <= int2ustd(0,14);                                                     
        else                                                                                       
          counter <= counter + int2ustd(1,14);                                                     
        end if;                                                                                    
      end if;                                                                                      
  end process n_sample_count;                                                                                  
                                                                                                
  -----------------------------------------------------------------------------------------------
  gen_sop_pulse : process(clk) is                                                     
    begin                                                                                        
      if(falling_edge(clk)) then                                                                  
        if(reset='1') then                                                                       
          master_sink_sop<='0';                                                                              
        elsif(counter(13 downto 0)=(13 downto 0 => '0')) then                                         
          if(master_sink_ena_reg='1') then                                                                   
            master_sink_sop<='1';                                                                        
          else                                                                   
            master_sink_sop<='0';                                                                   
          end if;                                                                              
        else                                                                                   
  	     master_sink_sop<='0';                                                                            
  	 end if;                                                                                
      end if;                                                                                  
  end process gen_sop_pulse;                                                                      
  -----------------------------------------------------------------------------------------------
  -- Generate master_sink_dav, master_source_dav input signals                            
  -----------------------------------------------------------------------------------------------
  gen_dav : process(clk) is                                                                      
    begin                                                                                         
      if(falling_edge(clk)) then                                                                   
        if(reset='1') then                                                                        
          master_sink_dav <= '0';                                                                 
          master_source_dav <= '0';                                                               
        else                                                                                      
          master_sink_dav <= '1';                                                                 
          master_source_dav <= '1';                                                               
        end if;                                                                                   
      end if;                                                                                     
  end process gen_dav;                                                                           
  		                                                                                           
	-----------------------------------------------------------------------------------------------
	-- Read input data from files                                                                  
	-----------------------------------------------------------------------------------------------
  testbench_i : process(clk) is                                                           
  file r_file		:	text open	read_mode	is "real_input.txt";                                     
	 file i_file		:	text open	read_mode	is "imag_input.txt";                                       
	 variable rdata		:	line;                                                                      
	 variable data_r	:	integer	;                                                                    
	 variable idata		:	line;                                                                      
	 variable data_i	:	integer	;                                                                    
	 begin                                                                                          
    if falling_edge(clk)	then                                                                     
	     if(reset='1') then                                                                         
        data_real_in<=int2ustd(0,16);                                                                    
        data_imag_in<=int2ustd(0,16);                                                                    
      else                                                                                       
        if not endfile(r_file)	then                                                             
          if(master_sink_ena_reg='1') then                                                                     
            readline(r_file,rdata);                                                              
            read(rdata,data_r);                                                                  
	           readline(i_file,idata);                                                              
	           read(idata,data_i);                                                                  
	           data_real_in<=int2ustd(data_r,16);                                                           
	           data_imag_in<=int2ustd(data_i,16);                                                           
	         else                                                                                   
	           data_real_in<=data_real_in;                                                                            
	           data_imag_in<=data_imag_in;                                                                            
	         end if;                                                                                
	       else                                                                                     
	         data_real_in<=int2ustd(0,16);                                                                  
	         data_imag_in<=int2ustd(0,16);                                                                  
	       end if;                                                                                  
      end if;                                                                                    
    end if;                                                                                    
  end process testbench_i;		                                                                 
 	                                                                                             
 ---------------------------------------------------------------------------------------------
 -- Write Real and Imginary Components and Block Exponent to Files                                               
 ---------------------------------------------------------------------------------------------
 	                                                                                             
  testbench_o : process(clk) is                                                            
  file ro_file		:	text open	write_mode	is "real_output_vhd.txt";                                
	 file io_file		:	text open	write_mode	is "imag_output_vhd.txt";                                
	 file eo_file		:	text open	write_mode	is "exponent_output_vhd.txt";                                
	 variable rdata		:	line;                                                                      
	 variable data_r	:	integer	;                                                                    
	 variable idata		:	line;                                                                      
	 variable data_i	:	integer	;                                                                    
	 variable edata		:	line;                                                                      
	 variable data_e	:	integer	;                                                                    
	 begin                                                                                          
   if falling_edge(clk)  then                                                                   
     if(master_source_ena='1' and reset='0') then                                                                       
       data_r := conv_integer(fft_real_out);                                                           
       data_i := conv_integer(fft_imag_out);                                                           
       data_e := conv_integer(exponent_out);                                                           
       write(rdata, data_r);                                                                  
       writeline(ro_file,rdata);                                                              
       write(idata, data_i);                                                                  
       writeline(io_file,idata);                                                              
       write(edata, data_e);                                                                  
       writeline(eo_file,edata);                                                              
     end if;                                                                                  
   end if;                                                                                    
 end process testbench_o;                                                                     
                                                                                                
 ---------------------------------------------------------------------------------------------
 -- FFT Component Instantiation                                                               
 ---------------------------------------------------------------------------------------------
dut : fft_small                                                                   
 port map(	                                                                    
           clk   => clk,                                                              
           reset => reset,                                                            
           inv_i => inv_i,                                                             
           data_real_in => data_real_in,                                                        
           data_imag_in => data_imag_in,                                                        
           fft_real_out	=> fft_real_out,                                                        
           fft_imag_out	=> fft_imag_out,                                                        
           exponent_out	=> exponent_out,                                                        
           master_sink_sop => master_sink_sop,                                                            
           master_sink_dav => master_sink_dav,                                                            
           master_sink_ena => master_sink_ena,                                                             
           master_source_ena => master_source_ena,                                                      
           master_source_dav => master_source_dav,                                                       
           master_source_sop => master_source_sop,                                                      
           master_source_eop => master_source_eop                                                      
);	                                                                                 
	 	                                                                                             
                                                                                                
end tb;