fft_small_tb.vhd

FFT 32k use VHDL MATLAB

--	Copyright (C) 1988-2004 Altera Corporation
--	Any megafunction design, and related net list (encrypted or decrypted),
--	support information, device programming or simulation file, and any other
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--	use of such megafunction design, net list, support information, device
--	programming or simulation file, or any other related documentation or
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--	trade secrets, or maskworks, embodied in any such megafunction design,
--	net list, support information, device programming or simulation file, or
--	any other related documentation or information provided by Altera or a
--	megafunction partner, remains with Altera, the megafunction partner, or
--	their respective licensors.  No other licenses, including any licenses
--	needed under any third party's intellectual property, are provided herein.

--       Altera FFT MegaCore ver 2.1.0 VHDL TESTBENCH
library ieee;                                                                                 
use ieee.std_logic_1164.all;                                                                    
use ieee.std_logic_signed.all;                                                                  
use ieee.std_logic_arith.all;                                                                   
use std.textio.all;                                                                             
entity fft_small_tb is                                                                            
end fft_small_tb;                                                                                 
                                                                                                
architecture tb of fft_small_tb is                                                                
                                                                                                
function int2ustd(value : integer; width : integer) return std_logic_vector is                 
-- convert integer to unsigned std_logicvector                                                 
 variable temp :   std_logic_vector(width-1 downto 0);                                          
	begin                                                                                          
	  if (width>0) then                                                                              
	    temp:=conv_std_logic_vector(conv_unsigned(value, width ), width);                          
	  end if ;                                                                                       
	return temp;                                                                                   
end int2ustd;                                                                                  
	                                                                                               
constant clk_time_step : time :=1 ns;                                                          
signal clk : std_logic;                                                                       
signal reset : std_logic;                                                                     
signal inv_i : std_logic;                                                                     
signal master_sink_sop : std_logic;                                                                       
signal master_sink_dav : std_logic;                                                                       
signal master_sink_ena : std_logic;                                                                       
signal master_sink_ena_reg : std_logic;                                                                   
signal data_real_in : std_logic_vector(15 downto 0);                                                
signal data_imag_in : std_logic_vector(15 downto 0);                                                
signal fft_real_out : std_logic_vector(15 downto 0);                                                
signal fft_imag_out : std_logic_vector(15 downto 0);                                                
signal exponent_out : std_logic_vector(5 downto 0);                                                
signal counter : std_logic_vector(13 downto 0);                                               
signal master_source_sop : std_logic;                                                                       
signal master_source_eop : std_logic;                                                                       
signal master_source_ena : std_logic;                                                                       
signal master_source_dav : std_logic;                                                                       
         	                                                                                     
--------------------------------------------------------------------------------------------                                      
-- FFT Component Declaration
--------------------------------------------------------------------------------------------                                      
component fft_small is                                                                     						 
 port (                                                                           
       clk	: in std_logic;                                                            
       reset	: in std_logic;                                                          
       inv_i	: in std_logic;                                                          
       data_real_in	: in std_logic_vector (15 downto 0);                             
       data_imag_in	: in std_logic_vector (15 downto 0);                             
       fft_real_out	: out std_logic_vector (15 downto 0);                            
       fft_imag_out	: out std_logic_vector (15 downto 0);                            
       exponent_out	: out std_logic_vector (5 downto 0);                            
       master_sink_dav	: in std_logic;                                                          
       master_sink_sop	: in std_logic;                                                          
       master_sink_ena	: out std_logic;                                                          
       master_source_dav	: in std_logic;                                                         
       master_source_ena	: out std_logic;                                                         
       master_source_sop	: out std_logic;                                                           
       master_source_eop	: out std_logic                                                           
);                                                                                 
end component;                                                                            
	                                                                                               
begin                                                                                           
	 -----------------------------------------------------------------------------------------------
  -- Reset Generation                                                                          
	 -----------------------------------------------------------------------------------------------
  reset <='1',                                                                                
          '0' after 92*clk_time_step;                                                          
	 -----------------------------------------------------------------------------------------------
  -- Clock Generation                                                                         
	 -----------------------------------------------------------------------------------------------
  clk_gen : process                                                                            
    begin                                                                                        
      loop                                                                                       
	       clk<='0' ,                                                                           
             '1'	after 5*clk_time_step;                                                            
	             wait for  10*clk_time_step;                                                              
	     end loop;                                                                                  
   end process clk_gen;                                                                                 
		                                                                                             
  -----------------------------------------------------------------------------------------------
  -- Set FFT Direction                                                                           
  -- '0' => FFT                                                                                  
  -- '1' => IFFT                                                                                 
  -----------------------------------------------------------------------------------------------
  inv_i <= '0';                                                                                  
  -----------------------------------------------------------------------------------------------
  -- All FFT MegaCore input signals are registered on the rising edge of the input clock, clk and 
  -- all FFT MegaCore output signals are output on the rising edge of the input clock, clk. 
  -- The testbench generates inputs and montitors output signals to and form the the core on the 
  -- negative edge of the clock avoid the necessity of zero-delay assumptions in post-fitting 
  -- simulation models and ensure expected behavior in all simulation flows.
  -----------------------------------------------------------------------------------------------
  -- Register output signal master_sink_ena on the negative edge of the clock 
  register_master_sink_ena : process(clk) is                                                                
   begin                                                                                         
     if(falling_edge(clk)) then                                                                   
       if(reset='1') then                                                                        
         master_sink_ena_reg <= '0';                                                               
       else                                                                                      
         master_sink_ena_reg <= master_sink_ena;                                                  
       end if;                                                                                   
     end if;                                                                                     
  end process register_master_sink_ena;                                                                     
                                                                                               
  -----------------------------------------------------------------------------------------------
  -- Generate a pulse on master_sink_sop every N clock cycles                 
  -----------------------------------------------------------------------------------------------
  n_sample_count : process(clk) is                                                       
    begin                                                                                         
      if(falling_edge(clk)) then