rel_clock.sim.rpt

来自「数字钟的程序」· RPT 代码 · 共 300 行 · 第 1/2 页

; |shuzizhong|minite1[1]            ; |shuzizhong|minite1[1]            ; padio            ;
; |shuzizhong|minite1[2]            ; |shuzizhong|minite1[2]            ; padio            ;
; |shuzizhong|minite1[3]            ; |shuzizhong|minite1[3]            ; padio            ;
; |shuzizhong|minite2[0]            ; |shuzizhong|minite2[0]            ; padio            ;
+-----------------------------------+-----------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                 ;
+-----------------------------------+-----------------------------------+------------------+
; Node Name                         ; Output Port Name                  ; Output Port Type ;
+-----------------------------------+-----------------------------------+------------------+
; |shuzizhong|\pro1:mhour11[1]      ; |shuzizhong|\pro1:mhour11[1]      ; regout           ;
; |shuzizhong|hour1~37              ; |shuzizhong|hour1~37              ; combout          ;
; |shuzizhong|\pro1:mhour21[2]      ; |shuzizhong|\pro1:mhour21[2]      ; regout           ;
; |shuzizhong|hour1~38              ; |shuzizhong|hour1~38              ; combout          ;
; |shuzizhong|\pro1:mhour21[3]      ; |shuzizhong|\pro1:mhour21[3]      ; regout           ;
; |shuzizhong|hour1~39              ; |shuzizhong|hour1~39              ; combout          ;
; |shuzizhong|hour2~40              ; |shuzizhong|hour2~40              ; combout          ;
; |shuzizhong|\pro1:mhour22[1]      ; |shuzizhong|\pro1:mhour22[1]      ; regout           ;
; |shuzizhong|hour2~41              ; |shuzizhong|hour2~41              ; combout          ;
; |shuzizhong|hour2~42              ; |shuzizhong|hour2~42              ; combout          ;
; |shuzizhong|hour2~43              ; |shuzizhong|hour2~43              ; combout          ;
; |shuzizhong|\pro1:msecond1[1]~9   ; |shuzizhong|\pro1:msecond1[1]~9   ; combout          ;
; |shuzizhong|msecond2~309          ; |shuzizhong|msecond2~309          ; combout          ;
; |shuzizhong|msecond2~309          ; |shuzizhong|\pro1:msecond2[3]     ; regout           ;
; |shuzizhong|\pro1:mminite2[0]~248 ; |shuzizhong|\pro1:mminite2[0]~248 ; combout          ;
; |shuzizhong|Equal3~31             ; |shuzizhong|Equal3~31             ; combout          ;
; |shuzizhong|mhour21~390           ; |shuzizhong|mhour21~390           ; combout          ;
; |shuzizhong|Add4~106              ; |shuzizhong|Add4~106              ; combout          ;
; |shuzizhong|pro1~113              ; |shuzizhong|pro1~113              ; combout          ;
; |shuzizhong|pro1~114              ; |shuzizhong|pro1~114              ; combout          ;
; |shuzizhong|Equal4~32             ; |shuzizhong|Equal4~32             ; combout          ;
; |shuzizhong|Add5~106              ; |shuzizhong|Add5~106              ; combout          ;
; |shuzizhong|Equal7~32             ; |shuzizhong|Equal7~32             ; combout          ;
; |shuzizhong|Add7~186              ; |shuzizhong|Add7~186              ; combout          ;
; |shuzizhong|Add7~187              ; |shuzizhong|Add7~187              ; combout          ;
; |shuzizhong|Add7~187              ; |shuzizhong|\pro1:mhour22[0]      ; regout           ;
; |shuzizhong|Add7~188              ; |shuzizhong|Add7~188              ; combout          ;
; |shuzizhong|Add7~188              ; |shuzizhong|\pro1:mhour22[3]      ; regout           ;
; |shuzizhong|Add7~189              ; |shuzizhong|Add7~189              ; combout          ;
; |shuzizhong|Add7~189              ; |shuzizhong|\pro1:mhour22[2]      ; regout           ;
; |shuzizhong|Add7~190              ; |shuzizhong|Add7~190              ; combout          ;
; |shuzizhong|pro1~115              ; |shuzizhong|pro1~115              ; combout          ;
; |shuzizhong|pro1~116              ; |shuzizhong|pro1~116              ; combout          ;
; |shuzizhong|Add6~181              ; |shuzizhong|Add6~181              ; combout          ;
; |shuzizhong|cout~524              ; |shuzizhong|cout~524              ; combout          ;
; |shuzizhong|set                   ; |shuzizhong|set                   ; combout          ;
; |shuzizhong|second2[3]            ; |shuzizhong|second2[3]            ; padio            ;
; |shuzizhong|minite2[2]            ; |shuzizhong|minite2[2]            ; padio            ;
; |shuzizhong|minite2[3]            ; |shuzizhong|minite2[3]            ; padio            ;
; |shuzizhong|hour1[0]              ; |shuzizhong|hour1[0]              ; padio            ;
; |shuzizhong|hour1[1]              ; |shuzizhong|hour1[1]              ; padio            ;
; |shuzizhong|hour1[2]              ; |shuzizhong|hour1[2]              ; padio            ;
; |shuzizhong|hour1[3]              ; |shuzizhong|hour1[3]              ; padio            ;
; |shuzizhong|hour2[0]              ; |shuzizhong|hour2[0]              ; padio            ;
; |shuzizhong|hour2[1]              ; |shuzizhong|hour2[1]              ; padio            ;
; |shuzizhong|hour2[2]              ; |shuzizhong|hour2[2]              ; padio            ;
; |shuzizhong|hour2[3]              ; |shuzizhong|hour2[3]              ; padio            ;
; |shuzizhong|cout                  ; |shuzizhong|cout                  ; padio            ;
+-----------------------------------+-----------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                 ;
+-----------------------------------+-----------------------------------+------------------+
; Node Name                         ; Output Port Name                  ; Output Port Type ;
+-----------------------------------+-----------------------------------+------------------+
; |shuzizhong|\pro1:mhour11[1]      ; |shuzizhong|\pro1:mhour11[1]      ; regout           ;
; |shuzizhong|hour1~37              ; |shuzizhong|hour1~37              ; combout          ;
; |shuzizhong|\pro1:mhour21[2]      ; |shuzizhong|\pro1:mhour21[2]      ; regout           ;
; |shuzizhong|hour1~38              ; |shuzizhong|hour1~38              ; combout          ;
; |shuzizhong|\pro1:mhour21[3]      ; |shuzizhong|\pro1:mhour21[3]      ; regout           ;
; |shuzizhong|hour1~39              ; |shuzizhong|hour1~39              ; combout          ;
; |shuzizhong|hour2~40              ; |shuzizhong|hour2~40              ; combout          ;
; |shuzizhong|\pro1:mhour22[1]      ; |shuzizhong|\pro1:mhour22[1]      ; regout           ;
; |shuzizhong|hour2~41              ; |shuzizhong|hour2~41              ; combout          ;
; |shuzizhong|hour2~42              ; |shuzizhong|hour2~42              ; combout          ;
; |shuzizhong|hour2~43              ; |shuzizhong|hour2~43              ; combout          ;
; |shuzizhong|\pro1:msecond1[1]~9   ; |shuzizhong|\pro1:msecond1[1]~9   ; combout          ;
; |shuzizhong|msecond2~309          ; |shuzizhong|msecond2~309          ; combout          ;
; |shuzizhong|msecond2~309          ; |shuzizhong|\pro1:msecond2[3]     ; regout           ;
; |shuzizhong|\pro1:mminite2[0]~248 ; |shuzizhong|\pro1:mminite2[0]~248 ; combout          ;
; |shuzizhong|Equal3~31             ; |shuzizhong|Equal3~31             ; combout          ;
; |shuzizhong|mhour21~390           ; |shuzizhong|mhour21~390           ; combout          ;
; |shuzizhong|Add4~106              ; |shuzizhong|Add4~106              ; combout          ;
; |shuzizhong|pro1~113              ; |shuzizhong|pro1~113              ; combout          ;
; |shuzizhong|pro1~114              ; |shuzizhong|pro1~114              ; combout          ;
; |shuzizhong|Equal4~32             ; |shuzizhong|Equal4~32             ; combout          ;
; |shuzizhong|Add5~106              ; |shuzizhong|Add5~106              ; combout          ;
; |shuzizhong|Equal7~32             ; |shuzizhong|Equal7~32             ; combout          ;
; |shuzizhong|Add7~186              ; |shuzizhong|Add7~186              ; combout          ;
; |shuzizhong|Add7~187              ; |shuzizhong|Add7~187              ; combout          ;
; |shuzizhong|Add7~187              ; |shuzizhong|\pro1:mhour22[0]      ; regout           ;
; |shuzizhong|Add7~188              ; |shuzizhong|Add7~188              ; combout          ;
; |shuzizhong|Add7~188              ; |shuzizhong|\pro1:mhour22[3]      ; regout           ;
; |shuzizhong|Add7~189              ; |shuzizhong|Add7~189              ; combout          ;
; |shuzizhong|Add7~189              ; |shuzizhong|\pro1:mhour22[2]      ; regout           ;
; |shuzizhong|Add7~190              ; |shuzizhong|Add7~190              ; combout          ;
; |shuzizhong|pro1~115              ; |shuzizhong|pro1~115              ; combout          ;
; |shuzizhong|pro1~116              ; |shuzizhong|pro1~116              ; combout          ;
; |shuzizhong|Add6~181              ; |shuzizhong|Add6~181              ; combout          ;
; |shuzizhong|cout~519              ; |shuzizhong|cout~519              ; combout          ;
; |shuzizhong|cout~524              ; |shuzizhong|cout~524              ; combout          ;
; |shuzizhong|set                   ; |shuzizhong|set                   ; combout          ;
; |shuzizhong|second2[3]            ; |shuzizhong|second2[3]            ; padio            ;
; |shuzizhong|minite2[1]            ; |shuzizhong|minite2[1]            ; padio            ;
; |shuzizhong|minite2[2]            ; |shuzizhong|minite2[2]            ; padio            ;
; |shuzizhong|minite2[3]            ; |shuzizhong|minite2[3]            ; padio            ;
; |shuzizhong|hour1[0]              ; |shuzizhong|hour1[0]              ; padio            ;
; |shuzizhong|hour1[1]              ; |shuzizhong|hour1[1]              ; padio            ;
; |shuzizhong|hour1[2]              ; |shuzizhong|hour1[2]              ; padio            ;
; |shuzizhong|hour1[3]              ; |shuzizhong|hour1[3]              ; padio            ;
; |shuzizhong|hour2[0]              ; |shuzizhong|hour2[0]              ; padio            ;
; |shuzizhong|hour2[1]              ; |shuzizhong|hour2[1]              ; padio            ;
; |shuzizhong|hour2[2]              ; |shuzizhong|hour2[2]              ; padio            ;
; |shuzizhong|hour2[3]              ; |shuzizhong|hour2[3]              ; padio            ;
; |shuzizhong|cout                  ; |shuzizhong|cout                  ; padio            ;
+-----------------------------------+-----------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon May 26 18:53:13 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off REL_clock -c REL_clock
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      46.81 %
Info: Number of transitions in simulation is 21120
Info: Vector file REL_clock.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Processing ended: Mon May 26 18:53:15 2008
    Info: Elapsed time: 00:00:03