dds_project.hif

用VHDL书写的DDS程序 里面有详细的注解

Version 7.2 Build 151 09/26/2007 SJ Full Version
38
2243
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
sum32
# storage
db|DDS_Project.(1).cnf
db|DDS_Project.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
sum32.vhd
b9edd7184611d79e6a52f3e9673b091
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(k)
31 downto 0
PARAMETER_STRING
USR
 constraint(out1)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
sum32:u1
}
# lmf
c:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
reg1
# storage
db|DDS_Project.(2).cnf
db|DDS_Project.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
reg1.vhd
37fe1098d45c7e61928863a26e6a762
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(d)
31 downto 0
PARAMETER_STRING
USR
 constraint(q)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
reg1:u2
}
# lmf
c:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
adder32
# storage
db|DDS_Project.(3).cnf
db|DDS_Project.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
adder32.vhd
c14a86e9aaed4e1274a6f1391d1a56f
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(n)
31 downto 0
PARAMETER_STRING
USR
 constraint(a)
31 downto 0
PARAMETER_STRING
USR
 constraint(out2)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
adder32:u3
}
# lmf
c:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
reg2
# storage
db|DDS_Project.(4).cnf
db|DDS_Project.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
reg2.vhd
f2e3bd29bc22a5b28e2a26802ad8e1d
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(e)
31 downto 0
PARAMETER_STRING
USR
 constraint(p)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
reg2:u4
}
# lmf
c:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
lpm_rom
# storage
db|DDS_Project.(6).cnf
db|DDS_Project.(6).cnf
# case_insensitive
# source_file
c:|altera|72|quartus|libraries|megafunctions|lpm_rom.tdf
b9b8a66b7e6565874587263c9736f56
6
# user_parameter {
LPM_WIDTH
10
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHAD
10
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
1024
PARAMETER_UNKNOWN
DEF
LPM_ADDRESS_CONTROL
registered
PARAMETER_UNKNOWN
USR
LPM_OUTDATA
unregistered
PARAMETER_UNKNOWN
USR
LPM_FILE
./data/sin_rom.mif
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclock
-1
3
da_data9
-1
3
da_data8
-1
3
da_data7
-1
3
da_data6
-1
3
da_data5
-1
3
da_data4
-1
3
da_data3
-1
3
da_data2
-1
3
da_data1
-1
3
da_data0
-1
3
address9
-1
3
address8
-1
3
address7
-1
3
address6
-1
3
address5
-1
3
address4
-1
3
address3
-1
3
address2
-1
3
address1
-1
3
address0
-1
3
}
# include_file {
c:|altera|72|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
c:|altera|72|quartus|libraries|megafunctions|aglobal72.inc
f39123b8592ab2dac019716e56b3ec18
}
# lmf
c:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
altrom
# storage
db|DDS_Project.(7).cnf
db|DDS_Project.(7).cnf
# case_insensitive
# source_file
c:|altera|72|quartus|libraries|megafunctions|altrom.tdf
b0531f5f6581a06f7455fc75fbffaab2
6
# user_parameter {
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
WIDTH
10
PARAMETER_UNKNOWN
USR
AD_WIDTH
10
PARAMETER_UNKNOWN
USR
NUMWORDS
1024
PARAMETER_UNKNOWN
USR
FILE
./data/sin_rom.mif
PARAMETER_UNKNOWN
USR
REGISTERINPUTMODE
ADDRESS_CONTROL
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
2048
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
SUPPRESS_MEMORY_CONVERSION_WARNINGS
OFF
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clocki
-1
3
address9
-1
3
address8
-1
3
address7
-1
3
address6
-1
3
address5
-1
3
address4
-1
3
address3
-1
3
address2
-1
3
address1
-1
3
address0
-1
3
}
# include_file {
c:|altera|72|quartus|libraries|megafunctions|aglobal72.inc
f39123b8592ab2dac019716e56b3ec18
c:|altera|72|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
c:|altera|72|quartus|libraries|others|maxplus2|memmodes.inc
44d4551a35f349f0dbacaf799d39950
c:|altera|72|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
c:|altera|72|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
c:|altera|72|quartus|libraries|megafunctions|altsyncram.inc
1b5760dd55919ddb45bfb2c0e896218b
}
# hierarchies {
romtab:u5|lpm_rom:lpm_rom_component|altrom:srom
}
# lmf
c:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
altsyncram
# storage
db|DDS_Project.(8).cnf
db|DDS_Project.(8).cnf
# case_insensitive
# source_file
c:|altera|72|quartus|libraries|megafunctions|altsyncram.tdf
56e814d9f431d4c82859865aa9372
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
10
PARAMETER_UNKNOWN
USR
WIDTHAD_A
10
PARAMETER_UNKNOWN
USR
NUMWORDS_A
1024
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
./data/sin_rom.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF