dds_project.sim.rpt

用VHDL书写的DDS程序 里面有详细的注解

; |dds|reg1:u2|q[28]        ; |dds|reg1:u2|q[28]               ; regout           ;
; |dds|reg1:u2|q[29]        ; |dds|reg1:u2|q[29]               ; regout           ;
; |dds|reg1:u2|q[30]        ; |dds|reg1:u2|q[30]               ; regout           ;
; |dds|reg1:u2|q[31]        ; |dds|reg1:u2|q[31]               ; regout           ;
; |dds|reg1:u2|q[4]         ; |dds|reg1:u2|q[4]                ; regout           ;
; |dds|reg1:u2|q[3]         ; |dds|reg1:u2|q[3]                ; regout           ;
; |dds|reg1:u2|q[2]         ; |dds|reg1:u2|q[2]                ; regout           ;
; |dds|reg1:u2|q[1]         ; |dds|reg1:u2|q[1]                ; regout           ;
; |dds|reg1:u2|q[0]         ; |dds|reg1:u2|q[0]                ; regout           ;
; |dds|phaseword[22]        ; |dds|phaseword[22]~corein        ; combout          ;
; |dds|en                   ; |dds|en~corein                   ; combout          ;
; |dds|phaseword[23]        ; |dds|phaseword[23]~corein        ; combout          ;
; |dds|phaseword[24]        ; |dds|phaseword[24]~corein        ; combout          ;
; |dds|phaseword[25]        ; |dds|phaseword[25]~corein        ; combout          ;
; |dds|phaseword[26]        ; |dds|phaseword[26]~corein        ; combout          ;
; |dds|phaseword[27]        ; |dds|phaseword[27]~corein        ; combout          ;
; |dds|phaseword[28]        ; |dds|phaseword[28]~corein        ; combout          ;
; |dds|phaseword[29]        ; |dds|phaseword[29]~corein        ; combout          ;
; |dds|phaseword[30]        ; |dds|phaseword[30]~corein        ; combout          ;
; |dds|phaseword[31]        ; |dds|phaseword[31]~corein        ; combout          ;
; |dds|phaseword[21]        ; |dds|phaseword[21]~corein        ; combout          ;
; |dds|freword[22]          ; |dds|freword[22]~corein          ; combout          ;
; |dds|reset                ; |dds|reset~corein                ; combout          ;
; |dds|phaseword[20]        ; |dds|phaseword[20]~corein        ; combout          ;
; |dds|freword[23]          ; |dds|freword[23]~corein          ; combout          ;
; |dds|freword[24]          ; |dds|freword[24]~corein          ; combout          ;
; |dds|freword[25]          ; |dds|freword[25]~corein          ; combout          ;
; |dds|freword[26]          ; |dds|freword[26]~corein          ; combout          ;
; |dds|freword[27]          ; |dds|freword[27]~corein          ; combout          ;
; |dds|freword[28]          ; |dds|freword[28]~corein          ; combout          ;
; |dds|freword[29]          ; |dds|freword[29]~corein          ; combout          ;
; |dds|freword[30]          ; |dds|freword[30]~corein          ; combout          ;
; |dds|freword[31]          ; |dds|freword[31]~corein          ; combout          ;
; |dds|phaseword[19]        ; |dds|phaseword[19]~corein        ; combout          ;
; |dds|phaseword[18]        ; |dds|phaseword[18]~corein        ; combout          ;
; |dds|phaseword[17]        ; |dds|phaseword[17]~corein        ; combout          ;
; |dds|freword[18]          ; |dds|freword[18]~corein          ; combout          ;
; |dds|phaseword[16]        ; |dds|phaseword[16]~corein        ; combout          ;
; |dds|phaseword[15]        ; |dds|phaseword[15]~corein        ; combout          ;
; |dds|phaseword[14]        ; |dds|phaseword[14]~corein        ; combout          ;
; |dds|freword[15]          ; |dds|freword[15]~corein          ; combout          ;
; |dds|phaseword[13]        ; |dds|phaseword[13]~corein        ; combout          ;
; |dds|phaseword[12]        ; |dds|phaseword[12]~corein        ; combout          ;
; |dds|freword[13]          ; |dds|freword[13]~corein          ; combout          ;
; |dds|phaseword[11]        ; |dds|phaseword[11]~corein        ; combout          ;
; |dds|phaseword[10]        ; |dds|phaseword[10]~corein        ; combout          ;
; |dds|freword[11]          ; |dds|freword[11]~corein          ; combout          ;
; |dds|phaseword[9]         ; |dds|phaseword[9]~corein         ; combout          ;
; |dds|phaseword[8]         ; |dds|phaseword[8]~corein         ; combout          ;
; |dds|phaseword[7]         ; |dds|phaseword[7]~corein         ; combout          ;
; |dds|phaseword[6]         ; |dds|phaseword[6]~corein         ; combout          ;
; |dds|freword[7]           ; |dds|freword[7]~corein           ; combout          ;
; |dds|phaseword[5]         ; |dds|phaseword[5]~corein         ; combout          ;
; |dds|phaseword[4]         ; |dds|phaseword[4]~corein         ; combout          ;
; |dds|phaseword[3]         ; |dds|phaseword[3]~corein         ; combout          ;
; |dds|freword[4]           ; |dds|freword[4]~corein           ; combout          ;
; |dds|phaseword[2]         ; |dds|phaseword[2]~corein         ; combout          ;
; |dds|freword[3]           ; |dds|freword[3]~corein           ; combout          ;
; |dds|phaseword[1]         ; |dds|phaseword[1]~corein         ; combout          ;
; |dds|freword[2]           ; |dds|freword[2]~corein           ; combout          ;
; |dds|phaseword[0]         ; |dds|phaseword[0]~corein         ; combout          ;
; |dds|freword[1]           ; |dds|freword[1]~corein           ; combout          ;
; |dds|freword[0]           ; |dds|freword[0]~corein           ; combout          ;
+---------------------------+----------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sun May 11 20:17:14 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off DDS_Project -c DDS_Project
Info: Using vector source file "D:/FPGA/DDS_Project/DDS_Waveform.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Warning: Found clock high time violation at 3.56 ns on register "|dds|adder32:u3|b[22]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|adder32:u3|b[23]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|adder32:u3|b[24]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|adder32:u3|b[25]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|adder32:u3|b[26]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|adder32:u3|b[27]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|adder32:u3|b[28]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|adder32:u3|b[29]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|adder32:u3|b[30]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|adder32:u3|b[31]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|sum32:u1|temp[22]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|sum32:u1|temp[23]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|sum32:u1|temp[24]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|sum32:u1|temp[25]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|sum32:u1|temp[26]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|sum32:u1|temp[27]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|sum32:u1|temp[28]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|sum32:u1|temp[29]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|sum32:u1|temp[30]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|sum32:u1|temp[31]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|sum32:u1|temp[21]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|sum32:u1|temp[20]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|sum32:u1|temp[19]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|sum32:u1|temp[18]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|sum32:u1|temp[17]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|sum32:u1|temp[16]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|sum32:u1|temp[15]"
Warning: Found clock high time violation at 3.56 ns on register "|dds|sum32:u1|temp[14]"
Warning: Found clock high time violation at 3.56 ns o