adder32.vhd

用VHDL书写的DDS程序 里面有详细的注解

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-- Project Name：  DDS_Project
-- File Name：	   adder32.vhd
-- Create Date:    20:02:10 2008-05-09
-- Engineer:	   Kun Yue
-- Target Device:  
-- Tool versions:  QuartusII 7.2
-- Description:    32位加法器
-- Additional Comments:   	
--				   n[31..0]----32位加数		en----使能信号		
--			       a[31..0]----32位被加数	out2[31..0]----32位和	
--			       clk----时钟信号
-- Revision: V1.0
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder32 is
	port(n: in std_logic_vector(31 downto 0);
         a: in std_logic_vector(31 downto 0);
         clk:in std_logic;
         en:in std_logic;
         out2:out std_logic_vector(31 downto 0));
end entity adder32;
architecture art of adder32 is
	signal b:std_logic_vector(31 downto 0);
	begin
	process(clk,en) is
		begin 
		if clk'event and clk='1'then
			if en='1'then
				b<=a+n;
			end if;
		end if;
		out2<=b;
end process;
end architecture art;