dds_project.tan.summary

用VHDL书写的DDS程序 里面有详细的注解

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.966 ns
From           : freword[6]
To             : sum32:u1|temp[31]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.690 ns
From           : romtab:u5|lpm_rom:lpm_rom_component|altrom:srom|altsyncram:rom_block|altsyncram_5l01:auto_generated|ram_block1a4~porta_address_reg9
To             : da_data[6]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.633 ns
From           : freword[2]
To             : sum32:u1|temp[2]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 329.38 MHz ( period = 3.036 ns )
From           : reg1:u2|q[6]
To             : adder32:u3|b[31]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------