reg1.vhd

用VHDL书写的DDS程序 里面有详细的注解

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-- Project Name：  DDS_Project
-- File Name：	   reg1.vhd
-- Create Date:    19:52:00 2008-05-09
-- Engineer:	   Kun Yue
-- Target Device:  
-- Tool versions:  QuartusII 7.2
-- Description:    寄存器1
-- Additional Comments:   	
--			   	d[31..0]----输入信号	q[31..0]----输出信号			
--				clk----时钟信号				
-- Revision: V1.0
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity reg1 is
   port(d: in std_logic_vector(31 downto 0);
        clk:in std_logic;
        q:out std_logic_vector(31 downto 0));
end entity reg1;
architecture art  of reg1 is
	begin
	process(clk) is
		begin 
		if clk'event and clk='1'then
			q<=d;
		end if;
end process;
end architecture art;