freqdivider.vhd

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--Used to divide the input CLK signal by a power of two.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FreqDivider is
	 -- determines the power of two by which to divide
	 generic ( division_factor: positive := 2);
    Port ( CLK : in std_logic;
           DIVIDED_CLK : out std_logic);
end FreqDivider;

architecture Behavioral of FreqDivider is
	signal counter: std_logic_vector(division_factor-1 downto 0);
begin
	process (CLK)
	begin
		if (CLK = '1' and CLK'event) then
			counter <= counter + '1';
		end if;
	end process;

	DIVIDED_CLK <= counter(division_factor-1);
end Behavioral;