sevensegdisplay.vhd

描述：LED示范、按钮及开关、视频输出、键入、含Xilinx PicoBlaze微处理器的存储器模块

--Used to control 4 seven-segment displays present on the extension board
--It modulates the 4 anode outputs and the brightness
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SevenSegDisplay is
	 generic ( pwm_precision: positive := 8 );
    Port ( CLK : in std_logic;
           RESET : in std_logic;
           SEG0_VALUE : in std_logic_vector(7 downto 0);
           SEG0_BRIGHTNESS : in std_logic_vector(pwm_precision - 1 downto 0);
           SEG1_VALUE : in std_logic_vector(7 downto 0);
           SEG1_BRIGHTNESS : in std_logic_vector(pwm_precision - 1 downto 0);
           SEG2_VALUE : in std_logic_vector(7 downto 0);
           SEG2_BRIGHTNESS : in std_logic_vector(pwm_precision - 1 downto 0);
           SEG3_VALUE : in std_logic_vector(7 downto 0);
           SEG3_BRIGHTNESS : in std_logic_vector(pwm_precision - 1 downto 0);
			  --The anodes
           ANODES : out std_logic_vector(3 downto 0);
			  --The segments
           LEDS : out std_logic_vector(7 downto 0));
end SevenSegDisplay;

architecture Behavioral of SevenSegDisplay is
	component LimitCounter is
		generic ( element_width: positive := pwm_precision);	
    	Port ( RESET : in std_logic;
             CLK : in std_logic;
		       SWITCH_LIMIT : in std_logic_vector(element_width-1 downto 0);           
             OUTPUT_SIGNAL : out std_logic);
	end component;

	component FreqDivider is	 
		 generic ( division_factor: positive := 2);
	    Port ( CLK : in std_logic;
	           DIVIDED_CLK : out std_logic);
	end component;

	signal anode_clock: std_logic;

	signal active_anode: std_logic_vector(1 downto 0);
	signal reset_anodes: std_logic_vector(3 downto 0);
	signal pwm_anodes: std_logic_vector(3 downto 0);
	
	signal show_leds: std_logic_vector(3 downto 0);		
begin	
	--Used to generate the stepping factor for the anode clock 
	AnodeDivider: FreqDivider 
		generic map ( division_factor => 8 )
		port map ( CLK, anode_clock);

	process (anode_clock, RESET)
	begin
		if RESET = '0' then
			if anode_clock = '1' and anode_clock'event then 
				active_anode <= active_anode + '1';
			end if;
		else
			active_anode <= "00";
		end if;
	end process;

	--Drive the anode
	with active_anode select
		pwm_anodes <= "0001" when "00",
			"0010" when "01",
			"0100" when "10",
			"1000" when others;	

	--Activate anodes only when PWM signal is on
	reset_anodes(0) <= pwm_anodes(0) and show_leds(0);
	reset_anodes(1) <= pwm_anodes(1) and show_leds(1);
	reset_anodes(2) <= pwm_anodes(2) and show_leds(2);
	reset_anodes(3) <= pwm_anodes(3) and show_leds(3);

	--The anodes are 0 active
	ANODES <= NOT(reset_anodes) when (RESET = '0') else "1111";

	--Modulate the outputs depending on the active anode
	with active_anode select
		LEDS <= SEG0_VALUE when "00",
			SEG1_VALUE when "01",
			SEG2_VALUE when "10",
			SEG3_VALUE when others;

	--Generate a PWM signal
	pwm0: LimitCounter port map ( RESET => RESET, CLK => CLK, SWITCH_LIMIT => SEG0_BRIGHTNESS, OUTPUT_SIGNAL => show_leds(0));
	pwm1: LimitCounter port map ( RESET => RESET, CLK => CLK, SWITCH_LIMIT => SEG1_BRIGHTNESS, OUTPUT_SIGNAL => show_leds(1));
	pwm2: LimitCounter port map ( RESET => RESET, CLK => CLK, SWITCH_LIMIT => SEG2_BRIGHTNESS, OUTPUT_SIGNAL => show_leds(2));
	pwm3: LimitCounter port map ( RESET => RESET, CLK => CLK, SWITCH_LIMIT => SEG3_BRIGHTNESS, OUTPUT_SIGNAL => show_leds(3));
end Behavioral;