📄 vgasyncgen.vhd
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--Syncron generator for VGA 640x480@60Hz.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity VGASyncGen is
Port ( CLK : in std_logic; --50 MHz clock
HS : out std_logic;
VS : out std_logic;
VIDEO_ON : out std_logic; --Shoul only display pixels while this
--is 1
X : out std_logic_vector(9 downto 0);
Y : out std_logic_vector(9 downto 0));
end VGASyncGen;
architecture Behavioral of VGASyncGen is
signal Pixel_Clock: std_logic;
signal horiz_sync, vert_sync : std_logic;
signal h_count, v_count: std_logic_vector(9 DOWNTO 0);
signal video_on_v, video_on_h : std_logic;
begin
HS <= horiz_sync;
VS <= vert_sync;
VIDEO_ON <= video_on_v and video_on_h;
--Divide the clock in half to get 50MHz
process (CLK)
begin
if (CLK'event) and (CLK = '1') then
Pixel_Clock <= not(Pixel_Clock);
end if;
end process;
process (Pixel_Clock)
begin
if (Pixel_Clock'event) and (Pixel_Clock = '0') then
--The horizontal pixel counter
if (h_count >= 799) then
h_count <= (others => '0');
else
h_count <= h_count + 1;
end if;
--The horizontal sync pulse
if (h_count <= 755) and (h_count >= 659) then
horiz_sync <= '0';
else
horiz_sync <= '1';
end if;
--Reset the vertical counter when appropiate
--(maximum number of lines reached)
if (v_count >= 524) and (h_count >= 699) then
v_count <= (others => '0');
elsif (h_count = 699) then
v_count <= v_count + 1;
end if;
--Vertical synch pulse (measured in lines, not pixels!)
if (v_count <= 494) and (v_count >= 493) then
vert_sync <= '0';
else
vert_sync <= '1';
end if;
--When appropiate, propageate the pixel / line count
if (h_count <= 639) then
video_on_h <= '1';
X <= h_count;
else
video_on_h <= '0';
end if;
if (v_count <= 479) then
video_on_v <= '1';
Y <= v_count;
else
video_on_v <= '0';
end if;
end if;
end process;
end Behavioral;
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