kcpsm.vhd

描述：LED示范、按钮及开关、视频输出、键入、含Xilinx PicoBlaze微处理器的存储器模块

  capture_flop: FDR
  port map ( D => interrupt,
             Q => clean_INT,
             R => reset,
             C => clk);

  pulse_lut: LUT4
  --translate_off
    generic map (INIT => X"0080")
  --translate_on
  port map( I0 => T_state,
            I1 => clean_INT,
            I2 => INT_enable,
            I3 => active_interrupt_internal,
             O => interrupt_pulse );

  active_flop: FDR
  port map ( D => interrupt_pulse,
             Q => active_interrupt_internal,
             R => reset,
             C => clk);

  -- Shadow flags

  shadow_carry_flop: FDE
  port map ( D => carry_flag,
             Q => shadow_carry,
            CE => active_interrupt_internal,
             C => clk);

  shadow_zero_flop: FDE
  port map ( D => zero_flag,
             Q => shadow_zero,
            CE => active_interrupt_internal,
             C => clk);
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of the Input and Output Strobes 
--	
-- Uses 3 LUTs and 2 flip-flops
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity IO_strobe_logic is
    Port (    instruction15 : in std_logic;
              instruction14 : in std_logic;
              instruction13 : in std_logic;
           active_interrupt : in std_logic;
                    T_state : in std_logic;
                      reset : in std_logic;
               write_strobe : out std_logic;
                read_strobe : out std_logic;
                        clk : in std_logic);
    end IO_strobe_logic;
--
architecture low_level_definition of IO_strobe_logic is
--
-- Internal signals
--
signal IO_type     : std_logic;
signal write_event : std_logic;
signal read_event  : std_logic;
--
-- Attributes to define LUT contents during implementation 
-- The information is repeated in the generic map for functional simulation
attribute INIT : string; 
attribute INIT of IO_type_lut : label is "8"; 
attribute INIT of write_lut   : label is "1000"; 
attribute INIT of read_lut    : label is "0100"; 
--
begin
  --
  IO_type_lut: LUT2
  --translate_off
    generic map (INIT => X"8")
  --translate_on
  port map( I0 => instruction13,
            I1 => instruction15,
             O => IO_type );

  write_lut: LUT4
  --translate_off
    generic map (INIT => X"1000")
  --translate_on
  port map( I0 => active_interrupt,
            I1 => T_state,
            I2 => instruction14,
            I3 => IO_type,
             O => write_event );

  write_flop: FDR
  port map ( D => write_event,
             Q => write_strobe,
             R => reset,
             C => clk);

  read_lut: LUT4
  --translate_off
    generic map (INIT => X"0100")
  --translate_on
  port map( I0 => active_interrupt,
            I1 => T_state,
            I2 => instruction14,
            I3 => IO_type,
             O => read_event );

  read_flop: FDR
  port map ( D => read_event,
             Q => read_strobe,
             R => reset,
             C => clk);
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of RAM for stack
--	 
-- This is a 16 location single port RAM of 8-bits to support the address range
-- of the program counter. The ouput is registered and the write enable is active low.
--
-- Total size 8 LUTs and 8 flip-flops.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity stack_ram is
    Port (        Din : in std_logic_vector(7 downto 0);
                 Dout : out std_logic_vector(7 downto 0);
                 addr : in std_logic_vector(3 downto 0);
            write_bar : in std_logic;
                  clk : in std_logic);
    end stack_ram;
--
architecture low_level_definition of stack_ram is
--
-- Internal signals
--
signal ram_out      : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
--
begin

  invert_enable: INV   -- Inverter should be implemented in the WE to RAM
  port map(  I => write_bar,
             O => write_enable);  
 
  bus_width_loop: for i in 0 to 7 generate
  --
  -- Attribute to define RAM contents during implementation 
  -- The information is repeated in the generic map for functional simulation
  --
  attribute INIT : string; 
  attribute INIT of stack_ram_bit : label is "0000"; 
  --
  begin

     stack_ram_bit: RAM16X1S
     -- translate_off
     generic map(INIT => X"0000")
     -- translate_on
     port map (    D => Din(i),
                  WE => write_enable,
                WCLK => clk,
                  A0 => addr(0),
                  A1 => addr(1),
                  A2 => addr(2),
                  A3 => addr(3),
                   O => ram_out(i));

     stack_ram_flop: FD
     port map ( D => ram_out(i),
                Q => Dout(i),
                C => clk);

  end generate bus_width_loop;
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of a 4-bit special counter for stack pointer
-- including instruction decoding.	
--
-- Total size 8 LUTs and 4 flip-flops.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity stack_counter is
    Port (        instruction15 : in std_logic;
                  instruction14 : in std_logic;
                  instruction13 : in std_logic;
                  instruction12 : in std_logic;
                   instruction9 : in std_logic;
                   instruction8 : in std_logic;
                   instruction7 : in std_logic;
                        T_state : in std_logic;
             flag_condition_met : in std_logic;
               active_interrupt : in std_logic;
                          reset : in std_logic;
                    stack_count : out std_logic_vector(3 downto 0);
                            clk : in std_logic);
    end stack_counter;
--
architecture low_level_definition of stack_counter is
--
-- Internal signals
--
signal not_interrupt     : std_logic;
signal count_value       : std_logic_vector(3 downto 0);
signal next_count        : std_logic_vector(3 downto 0);
signal count_carry       : std_logic_vector(2 downto 0);
signal half_count        : std_logic_vector(3 downto 0);
signal call_type         : std_logic;
signal valid_to_move     : std_logic;
signal pp_decode_a       : std_logic;
signal pp_decode_a_carry : std_logic;
signal pp_decode_b       : std_logic;
signal push_or_pop_type  : std_logic;
--
-- Attributes to define LUT contents during implementation 
-- The information is repeated in the generic map for functional simulation
attribute INIT : string; 
attribute INIT of valid_move_lut : label is "D"; 
attribute INIT of call_lut       : label is "0200"; 
attribute INIT of pp_a_lut       : label is "F2"; 
attribute INIT of pp_b_lut       : label is "10"; 
--
begin

  invert_interrupt: INV   -- Inverter should be implemented in the CE to flip flops
  port map(  I => active_interrupt,
             O => not_interrupt);  
  --
  -- Control logic decoding
  --
  valid_move_lut: LUT2
  --translate_off
    generic map (INIT => X"D")
  --translate_on
  port map( I0 => instruction12,
            I1 => flag_condition_met,
             O => valid_to_move );

  call_lut: LUT4
  --translate_off
    generic map (INIT => X"0200")
  --translate_on
  port map( I0 => instruction9,
            I1 => instruction13,
            I2 => instruction14,
            I3 => instruction15,
             O => call_type );


  pp_a_lut: LUT3
  --translate_off
    generic map (INIT => X"F2")
  --translate_on
  port map( I0 => instruction7,
            I1 => instruction8,
            I2 => instruction9,
             O => pp_decode_a );

  pp_b_lut: LUT3
  --translate_off
    generic map (INIT => X"10")
  --translate_on
  port map( I0 => instruction13,
            I1 => instruction14,
            I2 => instruction15,
             O => pp_decode_b );

  pp_a_muxcy: MUXCY
  port map( DI => '0',
            CI => '1',
             S => pp_decode_a,
             O => pp_decode_a_carry );

  en_b_cymux: MUXCY
  port map( DI => '0',
            CI => pp_decode_a_carry,
             S => pp_decode_b,
             O => push_or_pop_type  );

  count_width_loop: for i in 0 to 3 generate
  --
  -- The counter
  --
  begin

     register_bit: FDRE
     port map ( D => next_count(i),
                Q => count_value(i),
                R => reset,
               CE => not_interrupt,
                C => clk);

     lsb_count: if i=0 generate
	--
      -- Attribute to define LUT contents during implementation 
      -- The information is repeated in the generic map for functional simulation
      --
      attribute INIT : string; 
      attribute INIT of count_lut : label is "6555"; 
      --
	begin

       count_lut: LUT4
       --translate_off
       generic map (INIT => X"6555")
       --translate_on
       port map( I0 => count_value(i),
                 I1 => T_state,
                 I2 => valid_to_move,
                 I3 => push_or_pop_type,
                  O => half_count(i) );

       count_muxcy: MUXCY
       port map( DI => count_value(i),
                 CI => '0',
                  S => half_count(i),
                  O => count_carry(i));

       count_xor: XORCY
       port map( LI => half_count(i),
                 CI => '0',
                  O => next_count(i));
					   					   
	  end generate lsb_count;

     mid_count: if i>0 and i<3 generate
     --
     -- Attribute to define LUT contents during implementation 
     -- The information is repeated in the generic map for functional simulation
     --
     attribute INIT : string; 
     attribute INIT of count_lut : label is "A999"; 
     --
     begin

       count_lut: LUT4
       --translate_off
       generic map (INIT => X"A999")
       --translate_on
       port map( I0 => count_value(i),
                 I1 => T_state,
                 I2 => valid_to_move,
                 I3 => call_type,
                  O => half_count(i) );

       count_muxcy: MUXCY
       port map( DI => count_value(i),
                 CI => count_carry(i-1),
                  S => half_count(i),
                  O => count_carry(i));

       count_xor: XORCY
       port map( LI => half_count(i),
                 CI => count_carry(i-1),
                  O => next_count(i));

     end generate mid_count;

     msb_count: if i=3 generate
     --
     -- Attribute to define LUT contents during implementation 
     -- The information is repeated in the generic map for functional simulation
     --
     attribute INIT : string; 
     attribute INIT of count_lut : label is "A999"; 
     --
     begin

       count_lut: LUT4
       --translate_off
       generic map (INIT => X"A999")
       --translate_on
       port map( I0 => count_value(i),
                 I1 => T_state,
                 I2 => valid_to_move,
                 I3 => call_type,
                  O => half_count(i) );

       count_xor: XORCY
       port map( LI => half_count(i),
                 CI => count_carry(i-1),
                  O => next_count(i));

     end generate msb_count;

  end generate count_width_loop;

  stack_count <= count_value;
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit program counter
--	
-- This function provides the program counter and all decode logic.
--
-- Total size 21 LUTs and 8 flip-flops.
--