kcpsm.vhd

描述：LED示范、按钮及开关、视频输出、键入、含Xilinx PicoBlaze微处理器的存储器模块

    generic map (INIT => X"F4B0")
  --translate_on
  port map( I0 => instruction14,
            I1 => instruction15,
            I2 => carry_status,
            I3 => shadow_carry,
             O => next_carry_flag );

  carry_flag_flop: FDRE
  port map ( D => next_carry_flag,
             Q => carry_flag,
            CE => flag_enable,
             R => reset,
             C => clk);

--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit bus 2 to 1 multiplexer with built in select decode
--
-- Requires 9 LUTs.
--	 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity data_bus_mux2 is
    Port (         D1_bus : in std_logic_vector(7 downto 0);
                   D0_bus : in std_logic_vector(7 downto 0);
            instruction15 : in std_logic;
            instruction14 : in std_logic;
            instruction13 : in std_logic;
            instruction12 : in std_logic;
                    Y_bus : out std_logic_vector(7 downto 0));
    end data_bus_mux2;
--
architecture low_level_definition of data_bus_mux2 is
--
-- Internal signals
--
signal constant_sy_sel  : std_logic;
--
-- Attribute to define LUT contents during implementation 
-- The information is repeated in the generic map for functional simulation
attribute INIT : string; 
attribute INIT of decode_lut : label is "9800";
--
begin

  -- Forming decode signal

  decode_lut: LUT4
  --translate_off
    generic map (INIT => X"9800")
  --translate_on
  port map( I0 => instruction12,
            I1 => instruction13,
            I2 => instruction14,
            I3 => instruction15,
             O => constant_sy_sel );

  -- 2 to 1 bus multiplexer
 
  bus_width_loop: for i in 0 to 7 generate
  --
  -- Attribute to define LUT contents during implementation 
  -- The information is repeated in the generic map for functional simulation
  attribute INIT : string; 
  attribute INIT of mux_lut : label is "E4";
  --
  begin

    mux_lut: LUT3
    --translate_off
      generic map (INIT => X"E4")
    --translate_on
    port map( I0 => constant_sy_sel,
              I1 => D0_bus(i),
              I2 => D1_bus(i),
               O => Y_bus(i) );

  end generate bus_width_loop;
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of an 3-bit bus 2 to 1 multiplexer
--
-- Requires 3 LUTs.
--	 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity ALU_control_mux2 is
    Port (         D1_bus : in std_logic_vector(2 downto 0);
                   D0_bus : in std_logic_vector(2 downto 0);
            instruction15 : in std_logic;
                    Y_bus : out std_logic_vector(2 downto 0));
    end ALU_control_mux2;
--
architecture low_level_definition of ALU_control_mux2 is
--
begin

  -- 2 to 1 bus multiplexer
 
  bus_width_loop: for i in 0 to 2 generate
  --
  -- Attribute to define LUT contents during implementation 
  -- The information is repeated in the generic map for functional simulation
  attribute INIT : string; 
  attribute INIT of mux_lut : label is "E4";
  --
  begin

    mux_lut: LUT3
    --translate_off
      generic map (INIT => X"E4")
    --translate_on
    port map( I0 => instruction15,
              I1 => D0_bus(i),
              I2 => D1_bus(i),
               O => Y_bus(i) );

  end generate bus_width_loop;
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit dual port RAM with 16 locations
-- including write enable decode.
--	
-- This mode of distributed RAM requires 1 'slice' (2 LUTs)per bit.
-- Total for module 18 LUTs and 1 flip-flop.
-- 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity data_register_bank is
    Port (         address_A : in std_logic_vector(3 downto 0);
                   Din_A_bus : in std_logic_vector(7 downto 0);
                  Dout_A_bus : out std_logic_vector(7 downto 0);    
                   address_B : in std_logic_vector(3 downto 0);
                  Dout_B_bus : out std_logic_vector(7 downto 0);
               instruction15 : in std_logic; 
               instruction14 : in std_logic; 
               instruction13 : in std_logic; 
            active_interrupt : in std_logic; 
                     T_state : in std_logic; 
                         clk : in std_logic);
    end data_register_bank;
--
architecture low_level_definition of data_register_bank is
--
-- Internal signals
--
signal write_decode     : std_logic;
signal register_write   : std_logic;
signal register_enable  : std_logic;
--
-- Attribute to define LUT contents during implementation 
-- The information is repeated in the generic map for functional simulation
attribute INIT : string; 
attribute INIT of decode_lut : label is "1455";
attribute INIT of gating_lut : label is "8";
--
begin

  -- Forming decode signal

  decode_lut: LUT4
  --translate_off
    generic map (INIT => X"1455")
  --translate_on
  port map( I0 => active_interrupt,
            I1 => instruction13,
            I2 => instruction14,
            I3 => instruction15,
             O => write_decode );

  decode_pipe: FD
  port map ( D => write_decode,
             Q => register_write,
             C => clk);

  gating_lut: LUT2
  --translate_off
    generic map (INIT => X"8")
  --translate_on
  port map( I0 => T_state,
            I1 => register_write,
             O => register_enable );

  bus_width_loop: for i in 0 to 7 generate
  --
  -- Attribute to define RAM contents during implementation 
  -- The information is repeated in the generic map for functional simulation
  attribute INIT : string; 
  attribute INIT of data_register_bit : label is "0000"; 
  --
  begin

     data_register_bit: RAM16X1D
     -- translate_off
     generic map(INIT => X"0000")
     -- translate_on
     port map (       D => Din_A_bus(i),
                     WE => register_enable,
                   WCLK => clk,
                     A0 => address_A(0),
                     A1 => address_A(1),
                     A2 => address_A(2),
                     A3 => address_A(3),
                  DPRA0 => address_B(0),
                  DPRA1 => address_B(1),
                  DPRA2 => address_B(2),
                  DPRA3 => address_B(3),
                    SPO => Dout_A_bus(i),
                    DPO => Dout_B_bus(i));

  end generate bus_width_loop;
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of basic time T-state and clean reset
--	
-- This function forms the basic 2 cycle T-state control used by the processor.
-- It also forms a clean synchronous reset pulse that is long enough to ensure 
-- correct operation at start up and following a reset input.
-- It uses 1 LUT 3 flip-flops.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity T_state_and_Reset is
    Port (    reset_input : in std_logic;
           internal_reset : out std_logic;
                  T_state : out std_logic;
                      clk : in std_logic);
    end T_state_and_Reset;
--
architecture low_level_definition of T_state_and_Reset is
--
-- Internal signals
--
signal reset_delay1     : std_logic;
signal reset_delay2     : std_logic;
signal not_T_state      : std_logic;
signal internal_T_state : std_logic;
--
--
-- Attributes to define LUT contents during implementation 
-- The information is repeated in the generic map for functional simulation
attribute INIT : string; 
attribute INIT of invert_lut : label is "1"; 
--
begin
  --
  delay_flop1: FDS
  port map ( D => '0',
             Q => reset_delay1,
             S => reset_input,
             C => clk);

  delay_flop2: FDS
  port map ( D => reset_delay1,
             Q => reset_delay2,
             S => reset_input,
             C => clk);
    
  invert_lut: LUT1
  --translate_off
    generic map (INIT => X"1")
  --translate_on
  port map( I0 => internal_T_state,
             O => not_T_state );

  toggle_flop: FDR
  port map ( D => not_T_state,
             Q => internal_T_state,
             R => reset_delay2,
             C => clk);

  T_state <= internal_T_state;
  internal_reset <= reset_delay2;
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition Interrupt logic and shadow Flags.
--	
-- Decodes instructions which set and reset the interrupt enable flip-flop. 
-- Captures interrupt input and enables shadow flags
--
-- Total size 4 LUTs and 5 flip-flops.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity interrupt_logic is
    Port (           interrupt : in std_logic;
                 instruction15 : in std_logic;
                 instruction14 : in std_logic;
                 instruction13 : in std_logic;
                  instruction8 : in std_logic;
                  instruction5 : in std_logic;
                  instruction4 : in std_logic;
                     zero_flag : in std_logic;
                    carry_flag : in std_logic;
                   shadow_zero : out std_logic;
                  shadow_carry : out std_logic;
              active_interrupt : out std_logic;
                         reset : in std_logic;
                       T_state : in std_logic;
                           clk : in std_logic);
    end interrupt_logic;

--
architecture low_level_definition of interrupt_logic is
--
-- Internal signals
--
signal clean_INT                 : std_logic;
signal interrupt_pulse           : std_logic;
signal active_interrupt_internal : std_logic;
signal enable_a                  : std_logic;
signal enable_a_carry            : std_logic;
signal enable_b                  : std_logic;
signal update_enable             : std_logic;
signal INT_enable_value          : std_logic;
signal INT_enable                : std_logic;
--
-- Attributes to define LUT contents during implementation 
-- The information is repeated in the generic map for functional simulation
attribute INIT : string; 
attribute INIT of pulse_lut        : label is "0080";
attribute INIT of en_b_lut         : label is "ABAA";
attribute INIT of en_a_lut         : label is "AE";
attribute INIT of value_lut        : label is "4";
--
begin

  -- assignment of output signal

  active_interrupt <= active_interrupt_internal;

  --
  -- Decode instructions that set or reset interrupt enable
  --

  en_a_lut: LUT3
  --translate_off
    generic map (INIT => X"AE")
  --translate_on
  port map( I0 => active_interrupt_internal,
            I1 => instruction4,
            I2 => instruction8,
             O => enable_a );

  en_b_lut: LUT4
  --translate_off
    generic map (INIT => X"ABAA")
  --translate_on
  port map( I0 => active_interrupt_internal,
            I1 => instruction13,
            I2 => instruction14,
            I3 => instruction15,
             O => enable_b );

  en_a_muxcy: MUXCY
  port map( DI => '0',
            CI => '1',
             S => enable_a,
             O => enable_a_carry );

  en_b_cymux: MUXCY
  port map( DI => '0',
            CI => enable_a_carry,
             S => enable_b,
             O => update_enable );

  value_lut: LUT2
  --translate_off
    generic map (INIT => X"4")
  --translate_on
  port map( I0 => active_interrupt_internal,
            I1 => instruction5,
             O => INT_enable_value );

  enable_flop: FDRE
  port map ( D => INT_enable_value,
             Q => INT_enable,
            CE => update_enable,
             R => reset,
             C => clk);

  -- Capture interrupt signal and generate internal pulse if enabled