📄 kcpsm.vhd
字号:
--
-- This function uses 10 LUTs and associated carry logic.
-- The function contains an output pipeline register using 9 FDs.
--
-- Operation
--
-- Two input operands are added or subtracted.
-- An input carry bit can be included in the calculation.
-- An output carry is always generated.
-- Carry signals work in the positive sense at all times.
--
-- code1 code0 Bit injected
--
-- 0 0 ADD
-- 0 1 ADD with carry
-- 1 0 SUB
-- 1 1 SUB with carry
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity arithmetic_process is
Port ( first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
carry_in : in std_logic;
code1 : in std_logic;
code0 : in std_logic;
Y : out std_logic_vector(7 downto 0);
carry_out : out std_logic;
clk : in std_logic);
end arithmetic_process;
--
architecture low_level_definition of arithmetic_process is
--
-- Internal signals
--
signal carry_in_bit : std_logic;
signal carry_out_bit : std_logic;
signal modified_carry_out : std_logic;
signal half_addsub : std_logic_vector(7 downto 0);
signal full_addsub : std_logic_vector(7 downto 0);
signal carry_chain : std_logic_vector(6 downto 0);
--
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of carry_input_lut : label is "78";
attribute INIT of carry_output_lut : label is "6";
--
begin
--
-- Selection of the carry input to add/sub
--
carry_input_lut: LUT3
--translate_off
generic map (INIT => X"78")
--translate_on
port map( I0 => carry_in,
I1 => code0,
I2 => code1,
O => carry_in_bit );
--
-- Main add/sub
--
-- code1 Operation
--
-- 0 ADD Y <= first_operand + second_operand
-- 1 SUB Y <= first_operand - second_operand
--
bus_width_loop: for i in 0 to 7 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of arithmetic_lut : label is "96";
--
begin
lsb_carry: if i=0 generate
begin
arithmetic_carry: MUXCY
port map( DI => first_operand(i),
CI => carry_in_bit,
S => half_addsub(i),
O => carry_chain(i));
arithmetic_xor: XORCY
port map( LI => half_addsub(i),
CI => carry_in_bit,
O => full_addsub(i));
end generate lsb_carry;
mid_carry: if i>0 and i<7 generate
begin
arithmetic_carry: MUXCY
port map( DI => first_operand(i),
CI => carry_chain(i-1),
S => half_addsub(i),
O => carry_chain(i));
arithmetic_xor: XORCY
port map( LI => half_addsub(i),
CI => carry_chain(i-1),
O => full_addsub(i));
end generate mid_carry;
msb_carry: if i=7 generate
begin
arithmetic_carry: MUXCY
port map( DI => first_operand(i),
CI => carry_chain(i-1),
S => half_addsub(i),
O => carry_out_bit);
arithmetic_xor: XORCY
port map( LI => half_addsub(i),
CI => carry_chain(i-1),
O => full_addsub(i));
end generate msb_carry;
arithmetic_lut: LUT3
--translate_off
generic map (INIT => X"96")
--translate_on
port map( I0 => first_operand(i),
I1 => second_operand(i),
I2 => code1,
O => half_addsub(i));
pipeline_bit: FD
port map ( D => full_addsub(i),
Q => Y(i),
C => clk);
end generate bus_width_loop;
--
-- Modification to carry output and pipeline
--
carry_output_lut: LUT2
--translate_off
generic map (INIT => X"6")
--translate_on
port map( I0 => carry_out_bit,
I1 => code1,
O => modified_carry_out );
pipeline_bit: FD
port map ( D => modified_carry_out,
Q => carry_out,
C => clk);
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of the Zero and Carry Flags including decoding logic.
--
-- The ZERO value is detected using 2 LUTs and associated carry logic to
-- form a wired NOR gate. A further LUT selects the source for the ZERO flag
-- which is stored in an FDRE.
--
-- Definition of the Carry Flag
--
-- 3 LUTs and a pipeline flip-flop are used to select the source for the
-- CARRY flag which is stored in an FDRE.
--
-- Total size 11 LUTs and 5 flip-flops.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity flag_logic is
Port ( data : in std_logic_vector(7 downto 0);
instruction15 : in std_logic;
instruction14 : in std_logic;
instruction13 : in std_logic;
instruction12 : in std_logic;
instruction8 : in std_logic;
instruction6 : in std_logic;
code : in std_logic_vector(2 downto 0);
shadow_zero : in std_logic;
shadow_carry : in std_logic;
shift_rotate_carry : in std_logic;
add_sub_carry : in std_logic;
reset : in std_logic;
T_state : in std_logic;
zero_flag : out std_logic;
carry_flag : out std_logic;
clk : in std_logic);
end flag_logic;
--
architecture low_level_definition of flag_logic is
--
-- Internal signals
--
signal enable1a : std_logic;
signal enable1a_carry : std_logic;
signal enable1b : std_logic;
signal enable1b_carry : std_logic;
signal flag_en_op_sx_or_returni : std_logic;
signal enable2a : std_logic;
signal enable2a_carry : std_logic;
signal enable2b : std_logic;
signal enable2b_carry : std_logic;
signal flag_en_op_sx_sy_or_kk : std_logic;
signal flag_enable : std_logic;
signal lower_zero : std_logic;
signal upper_zero : std_logic;
signal lower_zero_carry : std_logic;
signal data_zero : std_logic;
signal next_zero_flag : std_logic;
signal carry_status : std_logic;
signal next_carry_flag : std_logic;
signal sX_op_decode : std_logic;
signal sX_operation : std_logic;
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of en1a_lut : label is "F002";
attribute INIT of en1b_lut : label is "4";
attribute INIT of en2a_lut : label is "10FF";
attribute INIT of en2b_lut : label is "FE";
attribute INIT of flag_enable_lut : label is "A8";
attribute INIT of lower_zero_lut : label is "0001";
attribute INIT of upper_zero_lut : label is "0001";
attribute INIT of zero_select_lut : label is "F4B0";
attribute INIT of operation_lut : label is "2000";
attribute INIT of carry_status_lut : label is "EC20";
attribute INIT of carry_select_lut : label is "F4B0";
--
begin
--
-- Decode instructions requiring flags to be enabled
--
en1a_lut: LUT4
--translate_off
generic map (INIT => X"F002")
--translate_on
port map( I0 => instruction6,
I1 => instruction8,
I2 => instruction12,
I3 => instruction14,
O => enable1a );
en1b_lut: LUT2
--translate_off
generic map (INIT => X"4")
--translate_on
port map( I0 => instruction13,
I1 => instruction15,
O => enable1b );
en1a_muxcy: MUXCY
port map( DI => '0',
CI => '1',
S => enable1a,
O => enable1a_carry );
en1b_cymux: MUXCY
port map( DI => '0',
CI => enable1a_carry,
S => enable1b,
O => enable1b_carry );
enable1_flop: FD
port map ( D => enable1b_carry,
Q => flag_en_op_sx_or_returni,
C => clk);
en2a_lut: LUT4
--translate_off
generic map (INIT => X"10FF")
--translate_on
port map( I0 => instruction12,
I1 => instruction13,
I2 => instruction14,
I3 => instruction15,
O => enable2a );
en2b_lut: LUT3
--translate_off
generic map (INIT => X"FE")
--translate_on
port map( I0 => code(0),
I1 => code(1),
I2 => code(2),
O => enable2b );
en2a_muxcy: MUXCY
port map( DI => '0',
CI => '1',
S => enable2a,
O => enable2a_carry );
en2b_cymux: MUXCY
port map( DI => '0',
CI => enable2a_carry,
S => enable2b,
O => enable2b_carry );
enable2_flop: FD
port map ( D => enable2b_carry,
Q => flag_en_op_sx_sy_or_kk,
C => clk);
flag_enable_lut: LUT3
--translate_off
generic map (INIT => X"A8")
--translate_on
port map( I0 => T_state,
I1 => flag_en_op_sx_sy_or_kk,
I2 => flag_en_op_sx_or_returni,
O => flag_enable );
--
-- Detect all bits in data are zero using wired NOR gate
--
lower_zero_lut: LUT4
--translate_off
generic map (INIT => X"0001")
--translate_on
port map( I0 => data(0),
I1 => data(1),
I2 => data(2),
I3 => data(3),
O => lower_zero );
upper_zero_lut: LUT4
--translate_off
generic map (INIT => X"0001")
--translate_on
port map( I0 => data(4),
I1 => data(5),
I2 => data(6),
I3 => data(7),
O => upper_zero );
lower_zero_muxcy: MUXCY
port map( DI => '0',
CI => '1',
S => lower_zero,
O => lower_zero_carry );
upper_zero_cymux: MUXCY
port map( DI => '0',
CI => lower_zero_carry,
S => upper_zero,
O => data_zero );
--
-- Select new zero status or the shaddow flag for a RETURNI
--
zero_select_lut: LUT4
--translate_off
generic map (INIT => X"F4B0")
--translate_on
port map( I0 => instruction14,
I1 => instruction15,
I2 => data_zero,
I3 => shadow_zero,
O => next_zero_flag );
zero_flag_flop: FDRE
port map ( D => next_zero_flag,
Q => zero_flag,
CE => flag_enable,
R => reset,
C => clk);
--
-- Select new carry status based on operation
--
operation_lut: LUT4
--translate_off
generic map (INIT => X"2000")
--translate_on
port map( I0 => instruction12,
I1 => instruction13,
I2 => instruction14,
I3 => instruction15,
O => sX_op_decode );
operation_pipe: FD
port map ( D => sX_op_decode,
Q => sX_operation,
C => clk);
carry_status_lut: LUT4
--translate_off
generic map (INIT => X"EC20")
--translate_on
port map( I0 => code(2),
I1 => sX_operation,
I2 => add_sub_carry,
I3 => shift_rotate_carry,
O => carry_status );
--
-- Select new carry status based on operationor the shaddow flag for a RETURNI
--
carry_select_lut: LUT4
--translate_off
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -