asyncrom_01.vhd

描述：LED示范、按钮及开关、视频输出、键入、含Xilinx PicoBlaze微处理器的存储器模块

--Asynchronous ROMs storing the instructions. Generated automatically
--For details please refer to the documentation
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity AsyncROM_00 is
    Port ( address : in std_logic_vector(7 downto 0);
           instruction : out std_logic_vector(15 downto 0));
end AsyncROM_00;

architecture Behavioral of AsyncROM_00 is
begin
	process (address)
	begin
		case (address) is
			when X"00" => instruction <= X"0001";
			when X"01" => instruction <= X"E000";

			when others => instruction <= (others => '0');
		end case;
	end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity AsyncROM_01 is
    Port ( address : in std_logic_vector(7 downto 0);
           instruction : out std_logic_vector(15 downto 0));
end AsyncROM_01;

architecture Behavioral of AsyncROM_01 is
begin
	process (address)
	begin
		case (address) is
			when X"00" => instruction <= X"0001";
			when X"01" => instruction <= X"E01C";
			when X"02" => instruction <= X"0020";
			when X"03" => instruction <= X"E01F";
			when X"04" => instruction <= X"007F";
			when X"05" => instruction <= X"E022";
			when X"06" => instruction <= X"00FF";
			when X"07" => instruction <= X"E025";
			when X"08" => instruction <= X"A011";
			when X"09" => instruction <= X"E008";
			when X"0A" => instruction <= X"E026";
			when X"0B" => instruction <= X"A002";
			when X"0C" => instruction <= X"E027";

			when others => instruction <= (others => '0');
		end case;
	end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity AsyncROM_10 is
    Port ( address : in std_logic_vector(7 downto 0);
           instruction : out std_logic_vector(15 downto 0));
end AsyncROM_10;

architecture Behavioral of AsyncROM_10 is
begin
	process (address)
	begin
		case (address) is
			when X"00" => instruction <= X"00FF";
			when X"01" => instruction <= X"E01C";
			when X"02" => instruction <= X"00FF";
			when X"03" => instruction <= X"E01F";
			when X"04" => instruction <= X"00FF";
			when X"05" => instruction <= X"E022";
			when X"06" => instruction <= X"00FF";
			when X"07" => instruction <= X"E025";
			when X"08" => instruction <= X"A111";
			when X"09" => instruction <= X"E108";
			when X"0A" => instruction <= X"E126";
			when X"0B" => instruction <= X"A003";
			when X"0C" => instruction <= X"C002";
			when X"0D" => instruction <= X"9513";
			when X"0E" => instruction <= X"E027";
			when X"0F" => instruction <= X"8108";
			when X"10" => instruction <= X"0001";
			when X"11" => instruction <= X"E027";
			when X"12" => instruction <= X"8108";
			when X"13" => instruction <= X"0002";
			when X"14" => instruction <= X"E027";

			when others => instruction <= (others => '0');
		end case;
	end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity AsyncROM_11 is
    Port ( address : in std_logic_vector(7 downto 0);
           instruction : out std_logic_vector(15 downto 0));
end AsyncROM_11;

architecture Behavioral of AsyncROM_11 is
begin
	process (address)
	begin
		case (address) is
			when X"00" => instruction <= X"0002";
			when X"01" => instruction <= X"E02E";
			when X"02" => instruction <= X"007F";
			when X"03" => instruction <= X"E02F";

			when others => instruction <= (others => '0');
		end case;
	end process;
end Behavioral;