📄 debouncer.vhd
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--component used to debounce an input signal
--the signal must be stable while the component counts
--from 0 to 2^wait_period to be propagated to the output port
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Debouncer is
generic ( wait_period: positive := 10);
Port ( CLK : in std_logic;
SIG_IN : in std_logic;
SIG_OUT : out std_logic);
end Debouncer;
architecture Behavioral of Debouncer is
signal counter: std_logic_vector(wait_period downto 0);
signal old_in_value: std_logic;
begin
process (CLK)
begin
if (CLK'event) and (CLK='1') then
if (SIG_IN = old_in_value) then
--if the input signal is stable, we have two possibilities:
--either we are ready to propagate it to the output port
--or we increment the counter waiting for it
if (counter(wait_period) = '1') then
SIG_OUT <= old_in_value;
else
counter <= counter + '1';
end if;
else
--input has changed, reset the counter to 0
counter <= (others => '0');
old_in_value <= SIG_IN;
end if;
end if;
end process;
end Behavioral;
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