videoram.vhd

描述：LED示范、按钮及开关、视频输出、键入、含Xilinx PicoBlaze微处理器的存储器模块

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity VideoRAM is
    Port ( CLK : std_logic;
	 		  EN : in std_logic;
			  RESET : in std_logic;
	 		  DO : out std_logic_vector(15 downto 0);
           DI : in std_logic_vector(15 downto 0);
           ADDR : in std_logic_vector(9 downto 0);
           WE : in std_logic);
end VideoRAM;

architecture Behavioral of VideoRAM is

signal DO_00, DO_01, DO_10, DO_11: std_logic_vector(15 downto 0); 
signal AD_00, AD_01, AD_10, AD_11: std_logic;
signal EN_00, EN_01, EN_10, EN_11: std_logic;
signal WE_00, WE_01, WE_10, WE_11: std_logic;

begin
	with ADDR(9 downto 8) select
		DO <= DO_00 when "00",
			DO_01 when "01",
			DO_10 when "10",
			DO_11 when others;

	with ADDR(9 downto 8) select
		AD_00 <= '1' when "00", '0' when others;
	with ADDR(9 downto 8) select
		AD_01 <= '1' when "01", '0' when others;
	with ADDR(9 downto 8) select
		AD_10 <= '1' when "10", '0' when others;
	with ADDR(9 downto 8) select
		AD_11 <= '1' when "11", '0' when others;

	EN_00 <= EN and AD_00;
	EN_01 <= EN and AD_01;
	EN_10 <= EN and AD_10;
	EN_11 <= EN and AD_11;

	WE_00 <= WE and AD_00;
	WE_01 <= WE and AD_01;
	WE_10 <= WE and AD_10;
	WE_11 <= WE and AD_11;

   RAMB4_S16_00 : RAMB4_S16
   port map (
      DO => DO_00,     -- 16-bit data output
      ADDR => ADDR(7 downto 0), -- 8-bit address input
      CLK => CLK,   -- Clock input
      DI => DI,     -- 16-bit data input
      EN => EN_00,     -- RAM enable input
      RST => RESET,   -- Synchronous reset input
      WE => WE_00      -- RAM write enable input
   );

   RAMB4_S16_01 : RAMB4_S16
   port map (
      DO => DO_01,     -- 16-bit data output
      ADDR => ADDR(7 downto 0), -- 8-bit address input
      CLK => CLK,   -- Clock input
      DI => DI,     -- 16-bit data input
      EN => EN_01,     -- RAM enable input
      RST => RESET,   -- Synchronous reset input
      WE => WE_01      -- RAM write enable input
   );

   RAMB4_S16_10 : RAMB4_S16
   port map (
      DO => DO_10,     -- 16-bit data output
      ADDR => ADDR(7 downto 0), -- 8-bit address input
      CLK => CLK,   -- Clock input
      DI => DI,     -- 16-bit data input
      EN => EN_10,     -- RAM enable input
      RST => RESET,   -- Synchronous reset input
      WE => WE_10      -- RAM write enable input
   );

   RAMB4_S16_11 : RAMB4_S16
   port map (
      DO => DO_11,     -- 16-bit data output
      ADDR => ADDR(7 downto 0), -- 8-bit address input
      CLK => CLK,   -- Clock input
      DI => DI,     -- 16-bit data input
      EN => EN_11,     -- RAM enable input
      RST => RESET,   -- Synchronous reset input
      WE => WE_11      -- RAM write enable input
   );
end Behavioral;