limitcounter.vhd

描述：LED示范、按钮及开关、视频输出、键入、含Xilinx PicoBlaze微处理器的存储器模块

--Component, which counts from 0 to UPPER_LIMIT and changes OUTPUT_SIGNAL
--from 1 to 0 when SWITCH_LIMIT is reached
--Intended pourpuse: to be used in a PWM modulator
--The bit width of the counter / signals may be customized

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity LimitCounter is
	 generic ( element_width: positive := 8);
    Port ( RESET : in std_logic;
           CLK : in std_logic;
			  SWITCH_LIMIT : in std_logic_vector(element_width-1 downto 0);           
           OUTPUT_SIGNAL : out std_logic);
end LimitCounter;

architecture Behavioral of LimitCounter is
	signal count_value: std_logic_vector(element_width-1 downto 0);
	signal reset_output: std_logic;
begin
	process (RESET, CLK)
	begin
		if RESET = '0' then
			if (CLK = '1' and CLK'event) then 
				count_value <= count_value + '1';								
			end if;
		else 
			--reset the counter
			count_value <= (others => '0');			
		end if;
	end process;		
	
	--Make sure that the output is 0 when the filling factor is 0%
	--And that the output is 1 all the time when the filling factor is 100%
	--(This hack will result that a special filling factor can be reached
	--with two distinct values)
	reset_output <= '1' when (count_value <= SWITCH_LIMIT) and (SWITCH_LIMIT > 0) else '0';		

	--fast forward the reset to the output
   OUTPUT_SIGNAL <=  reset_output when (RESET = '0') else '0';
end Behavioral;