dportvidram.vhd

描述：LED示范、按钮及开关、视频输出、键入、含Xilinx PicoBlaze微处理器的存储器模块

--Dual port synchronous RAM for character data / attributes
--Port A is R/W, port B is just R
--Uses predefined components to be synthetized as block-ram
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity DPortVidRam is
    Port ( ADDRESS_A : in std_logic_vector(9 downto 0);
           ADDRESS_B : in std_logic_vector(9 downto 0);
           DATA_READ_A : out std_logic_vector(15 downto 0);
           DATA_READ_B : out std_logic_vector(15 downto 0);
           DATA_WRITE_A : in std_logic_vector(15 downto 0);
           ENABLE_A : in std_logic;
           ENABLE_B : in std_logic;
           WRITE_STROBE_A : in std_logic;
           CLK : in std_logic;
           RESET : in std_logic);
end DPortVidRam;

architecture Behavioral of DPortVidRam is

signal DOA_00, DOA_01, DOA_10, DOA_11: std_logic_vector(15 downto 0); 
signal DOB_00, DOB_01, DOB_10, DOB_11: std_logic_vector(15 downto 0); 

signal ADA_00, ADA_01, ADA_10, ADA_11: std_logic;
signal ENA_00, ENA_01, ENA_10, ENA_11: std_logic;
signal WEA_00, WEA_01, WEA_10, WEA_11: std_logic;

signal ADB_00, ADB_01, ADB_10, ADB_11: std_logic;
signal ENB_00, ENB_01, ENB_10, ENB_11: std_logic;

begin
	--Output MUXs
	with ADDRESS_A(9 downto 8) select
		DATA_READ_A <= DOA_00 when "00",
			DOA_01 when "01",
			DOA_10 when "10",
			DOA_11 when others;

	with ADDRESS_B(9 downto 8) select
		DATA_READ_B <= DOB_00 when "00",
			DOB_01 when "01",
			DOB_10 when "10",
			DOB_11 when others;

	--The "chip select" signals for the A port
	with ADDRESS_A(9 downto 8) select
		ADA_00 <= '1' when "00", '0' when others;
	with ADDRESS_A(9 downto 8) select
		ADA_01 <= '1' when "01", '0' when others;
	with ADDRESS_A(9 downto 8) select
		ADA_10 <= '1' when "10", '0' when others;
	with ADDRESS_A(9 downto 8) select
		ADA_11 <= '1' when "11", '0' when others;

	ENA_00 <= ENABLE_A and ADA_00;
	ENA_01 <= ENABLE_A and ADA_01;
	ENA_10 <= ENABLE_A and ADA_10;
	ENA_11 <= ENABLE_A and ADA_11;

	WEA_00 <= WRITE_STROBE_A and ADA_00;
	WEA_01 <= WRITE_STROBE_A and ADA_01;
	WEA_10 <= WRITE_STROBE_A and ADA_10;
	WEA_11 <= WRITE_STROBE_A and ADA_11;

	--The "chip select" signals for the B port
	with ADDRESS_B(9 downto 8) select
		ADB_00 <= '1' when "00", '0' when others;
	with ADDRESS_B(9 downto 8) select
		ADB_01 <= '1' when "01", '0' when others;
	with ADDRESS_B(9 downto 8) select
		ADB_10 <= '1' when "10", '0' when others;
	with ADDRESS_B(9 downto 8) select
		ADB_11 <= '1' when "11", '0' when others;

	ENB_00 <= ENABLE_B and ADB_00;
	ENB_01 <= ENABLE_B and ADB_01;
	ENB_10 <= ENABLE_B and ADB_10;
	ENB_11 <= ENABLE_B and ADB_11;

   RAMB4_S16_S16_00 : RAMB4_S16_S16
   port map (DOA_00, DOB_00, ADDRESS_A(7 downto 0), ADDRESS_B(7 downto 0),
		CLK, CLK, DATA_WRITE_A, "0000000000000000",
		ENA_00, ENB_00, RESET, RESET, WEA_00, '0');

   RAMB4_S16_S16_01 : RAMB4_S16_S16
   port map (DOA_01, DOB_01, ADDRESS_A(7 downto 0), ADDRESS_B(7 downto 0),
		CLK, CLK, DATA_WRITE_A, "0000000000000000",
		ENA_01, ENB_01, RESET, RESET, WEA_01, '0');

   RAMB4_S16_S16_10 : RAMB4_S16_S16
   port map (DOA_10, DOB_10, ADDRESS_A(7 downto 0), ADDRESS_B(7 downto 0),
		CLK, CLK, DATA_WRITE_A, "0000000000000000",
		ENA_10, ENB_10, RESET, RESET, WEA_10, '0');

   RAMB4_S16_S16_11 : RAMB4_S16_S16
   port map (DOA_11, DOB_11, ADDRESS_A(7 downto 0), ADDRESS_B(7 downto 0),
		CLK, CLK, DATA_WRITE_A, "0000000000000000",
		ENA_11, ENB_11, RESET, RESET, WEA_11, '0');
end Behavioral;