📄 embedded_kcpsm.vhd
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--
-- EMBEDDED_KCPSM.VHD
--
-- Ken Chapman - Xilinx Ltd - October 2002
--
-- This file instantiates the KCPSM processor macro and connects the
-- program ROM.
--
-- NOTE: The name of the program ROM will probably need to be changed to
-- reflect the name of the program (PSM) file applied to the assembler.
--
-- Modified by Balazs Attila-Mihaly to include support for multiple program ROMs
-- The index of the selected ROM is latched while reset is active
------------------------------------------------------------------------------------
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
------------------------------------------------------------------------------------
--
--
entity embedded_kcpsm is
Port ( port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
read_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
reset : in std_logic;
clk : in std_logic;
switches : in std_logic_vector(7 downto 0));
end embedded_kcpsm;
--
------------------------------------------------------------------------------------
--
-- Start of test achitecture
--
architecture connectivity of embedded_kcpsm is
--
------------------------------------------------------------------------------------
--
-- declaration of KCPSM
--
component kcpsm
Port ( address : out std_logic_vector(7 downto 0);
instruction : in std_logic_vector(15 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
--
-- declaration of program ROM
--
component AsyncROM_00 is
Port ( address : in std_logic_vector(7 downto 0);
instruction : out std_logic_vector(15 downto 0));
end component;
component AsyncROM_01 is
Port ( address : in std_logic_vector(7 downto 0);
instruction : out std_logic_vector(15 downto 0));
end component;
component AsyncROM_10 is
Port ( address : in std_logic_vector(7 downto 0);
instruction : out std_logic_vector(15 downto 0));
end component;
component AsyncROM_11 is
Port ( address : in std_logic_vector(7 downto 0);
instruction : out std_logic_vector(15 downto 0));
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used to connect KCPSM to program ROM
--
signal address : std_logic_vector(7 downto 0);
signal instruction : std_logic_vector(15 downto 0);
signal switch_count : std_logic_vector(1 downto 0);
signal instruction_00, instruction_01, instruction_10, instruction_11 : std_logic_vector(15 downto 0);
--
------------------------------------------------------------------------------------
--
-- Start of test circuit description
--
begin
processor: kcpsm
port map( address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
reset => reset,
clk => clk);
--------------------------------------------------------------------
-- The possible programs
AS00 : AsyncROM_00 port map ( address, instruction_00 );
AS01 : AsyncROM_01 port map ( address, instruction_01 );
AS10 : AsyncROM_10 port map ( address, instruction_10 );
AS11 : AsyncROM_11 port map ( address, instruction_11 );
-- Latch to store which program will be used
process (reset, switches)
begin
if (RESET = '1') then
switch_count <= switches(1 downto 0);
end if;
end process;
-- MUX
with switch_count select
instruction <= instruction_11 when "11",
instruction_01 when "01",
instruction_10 when "10",
instruction_00 when others;
end connectivity;
------------------------------------------------------------------------------------
--
-- END OF FILE EMBEDDED_KCPSM.VHD
--
------------------------------------------------------------------------------------
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