📄 syncroms.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity prog_rom_00 is
Port ( address : in std_logic_vector(7 downto 0);
instruction : out std_logic_vector(15 downto 0);
clk : in std_logic);
end prog_rom_00;
architecture low_level_definition of prog_rom_00 is
begin
process (clk)
begin
if (clk'event) and (clk = '1') then
case (address) is
when X"00" => instruction <= X"0001";
when X"01" => instruction <= X"E000";
when X"02" => instruction <= X"00FF";
when X"03" => instruction <= X"E022";
when X"04" => instruction <= X"00FF";
when X"05" => instruction <= X"E025";
when X"06" => instruction <= X"0000";
when X"07" => instruction <= X"E027";
when X"08" => instruction <= X"0020";
when X"09" => instruction <= X"E01C";
when X"0A" => instruction <= X"0020";
when X"0B" => instruction <= X"E01F";
when X"0C" => instruction <= X"A111";
when X"0D" => instruction <= X"E108";
when X"0E" => instruction <= X"E126";
when X"0F" => instruction <= X"A002";
when X"10" => instruction <= X"1001";
when X"11" => instruction <= X"951F";
when X"12" => instruction <= X"A002";
when X"13" => instruction <= X"1002";
when X"14" => instruction <= X"9523";
when X"15" => instruction <= X"A002";
when X"16" => instruction <= X"1004";
when X"17" => instruction <= X"9527";
when X"18" => instruction <= X"A002";
when X"19" => instruction <= X"1008";
when X"1A" => instruction <= X"952B";
when X"1B" => instruction <= X"A002";
when X"1C" => instruction <= X"1010";
when X"1D" => instruction <= X"952F";
when X"1E" => instruction <= X"8108";
when X"1F" => instruction <= X"E12E";
when X"20" => instruction <= X"0010";
when X"21" => instruction <= X"E02F";
when X"22" => instruction <= X"8133";
when X"23" => instruction <= X"E12E";
when X"24" => instruction <= X"0040";
when X"25" => instruction <= X"E02F";
when X"26" => instruction <= X"8133";
when X"27" => instruction <= X"E12E";
when X"28" => instruction <= X"0060";
when X"29" => instruction <= X"E02F";
when X"2A" => instruction <= X"8133";
when X"2B" => instruction <= X"E12E";
when X"2C" => instruction <= X"0080";
when X"2D" => instruction <= X"E02F";
when X"2E" => instruction <= X"8133";
when X"2F" => instruction <= X"E12E";
when X"30" => instruction <= X"00FE";
when X"31" => instruction <= X"E02F";
when X"32" => instruction <= X"8133";
when X"33" => instruction <= X"A02F";
when X"34" => instruction <= X"E027";
when X"35" => instruction <= X"2000";
when X"36" => instruction <= X"9108";
when X"37" => instruction <= X"00FF";
when X"38" => instruction <= X"E01C";
when X"39" => instruction <= X"00FF";
when X"3A" => instruction <= X"E01F";
when X"3B" => instruction <= X"8133";
when others => instruction <= X"0000";
end case;
end if;
end process;
end low_level_definition;
--
-- Definition of a single port ROM for KCPSM program defined by prog_rom.psm
-- and assmbled using KCPSM assembler.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity prog_rom_01 is
Port ( address : in std_logic_vector(7 downto 0);
instruction : out std_logic_vector(15 downto 0);
clk : in std_logic);
end prog_rom_01;
architecture low_level_definition of prog_rom_01 is
begin
process (clk)
begin
if (clk'event) and (clk = '1') then
case (address) is
when X"00" => instruction <= X"0001";
when X"01" => instruction <= X"E01C";
when X"02" => instruction <= X"0020";
when X"03" => instruction <= X"E01F";
when X"04" => instruction <= X"007F";
when X"05" => instruction <= X"E022";
when X"06" => instruction <= X"00FF";
when X"07" => instruction <= X"E025";
when X"08" => instruction <= X"A011";
when X"09" => instruction <= X"E008";
when X"0A" => instruction <= X"E026";
when X"0B" => instruction <= X"A002";
when X"0C" => instruction <= X"E027";
when X"0D" => instruction <= X"8108";
when others => instruction <= X"0000";
end case;
end if;
end process;
end low_level_definition;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity prog_rom_10 is
Port ( address : in std_logic_vector(7 downto 0);
instruction : out std_logic_vector(15 downto 0);
clk : in std_logic);
end prog_rom_10;
architecture low_level_definition of prog_rom_10 is
begin
process (clk)
begin
if (clk'event) and (clk = '1') then
case (address) is
when X"00" => instruction <= X"0000";
when X"01" => instruction <= X"0100";
when X"02" => instruction <= X"AE2C";
when X"03" => instruction <= X"E030";
when X"04" => instruction <= X"E131";
when X"05" => instruction <= X"0700";
when X"06" => instruction <= X"E732";
when X"07" => instruction <= X"E733";
when X"08" => instruction <= X"4001";
when X"09" => instruction <= X"C700";
when X"0A" => instruction <= X"6728";
when X"0B" => instruction <= X"9503";
when X"0C" => instruction <= X"0000";
when X"0D" => instruction <= X"4101";
when X"0E" => instruction <= X"C710";
when X"0F" => instruction <= X"670F";
when X"10" => instruction <= X"9503";
when X"11" => instruction <= X"0005";
when X"12" => instruction <= X"E030";
when X"13" => instruction <= X"0005";
when X"14" => instruction <= X"E031";
when X"15" => instruction <= X"0710";
when X"16" => instruction <= X"0148";
when X"17" => instruction <= X"833A";
when X"18" => instruction <= X"0720";
when X"19" => instruction <= X"0165";
when X"1A" => instruction <= X"833A";
when X"1B" => instruction <= X"0730";
when X"1C" => instruction <= X"016C";
when X"1D" => instruction <= X"833A";
when X"1E" => instruction <= X"0740";
when X"1F" => instruction <= X"016C";
when X"20" => instruction <= X"833A";
when X"21" => instruction <= X"0750";
when X"22" => instruction <= X"016F";
when X"23" => instruction <= X"833A";
when X"24" => instruction <= X"0700";
when X"25" => instruction <= X"0120";
when X"26" => instruction <= X"833A";
when X"27" => instruction <= X"0760";
when X"28" => instruction <= X"0157";
when X"29" => instruction <= X"833A";
when X"2A" => instruction <= X"0770";
when X"2B" => instruction <= X"016F";
when X"2C" => instruction <= X"833A";
when X"2D" => instruction <= X"0780";
when X"2E" => instruction <= X"0172";
when X"2F" => instruction <= X"833A";
when X"30" => instruction <= X"0790";
when X"31" => instruction <= X"016C";
when X"32" => instruction <= X"833A";
when X"33" => instruction <= X"07A0";
when X"34" => instruction <= X"0164";
when X"35" => instruction <= X"833A";
when X"36" => instruction <= X"07B0";
when X"37" => instruction <= X"0121";
when X"38" => instruction <= X"833A";
when X"39" => instruction <= X"8139";
when X"3A" => instruction <= X"E030";
when X"3B" => instruction <= X"E132";
when X"3C" => instruction <= X"E733";
when X"3D" => instruction <= X"4001";
when X"3E" => instruction <= X"8080";
when others => instruction <= X"0000";
end case;
end if;
end process;
end low_level_definition;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity prog_rom_11 is
Port ( address : in std_logic_vector(7 downto 0);
instruction : out std_logic_vector(15 downto 0);
clk : in std_logic);
end prog_rom_11;
architecture low_level_definition of prog_rom_11 is
begin
process (clk)
begin
if (clk'event) and (clk = '1') then
case (address) is
when X"00" => instruction <= X"0000";
when X"01" => instruction <= X"0100";
when X"02" => instruction <= X"AE2C";
when X"03" => instruction <= X"CFE0";
when X"04" => instruction <= X"DF06";
when X"05" => instruction <= X"DF06";
when X"06" => instruction <= X"DF06";
when X"07" => instruction <= X"DF06";
when X"08" => instruction <= X"CEF4";
when X"09" => instruction <= X"E030";
when X"0A" => instruction <= X"E131";
when X"0B" => instruction <= X"C700";
when X"0C" => instruction <= X"D70E";
when X"0D" => instruction <= X"C714";
when X"0E" => instruction <= X"C7E4";
when X"0F" => instruction <= X"E734";
when X"10" => instruction <= X"C710";
when X"11" => instruction <= X"D70E";
when X"12" => instruction <= X"C704";
when X"13" => instruction <= X"C7E4";
when X"14" => instruction <= X"E735";
when X"15" => instruction <= X"07DF";
when X"16" => instruction <= X"E732";
when X"17" => instruction <= X"4001";
when X"18" => instruction <= X"C700";
when X"19" => instruction <= X"6728";
when X"1A" => instruction <= X"9509";
when X"1B" => instruction <= X"0000";
when X"1C" => instruction <= X"4101";
when X"1D" => instruction <= X"C710";
when X"1E" => instruction <= X"670F";
when X"1F" => instruction <= X"9509";
when X"20" => instruction <= X"8100";
when others => instruction <= X"0000";
end case;
end if;
end process;
end low_level_definition;⌨️ 快捷键说明
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