cdiv.twr

这个是国外大学的项目代码

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Release 7.1.04i Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

C:/Program Files/Xilinx/bin/nt/trce.exe -ise
e:\work\digilentinc\xiphard\XipHard.ise -intstyle ise -e 3 -l 3 -s 6 -xml cdiv
cdiv.ncd -o cdiv.twr cdiv.pcf


Design file:              cdiv.ncd
Physical constraint file: cdiv.pcf
Device,speed:             xc2s200e,-6 (PRODUCTION 1.18 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock CLK
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
DI<0>       |    7.135(R)|   -6.577(R)|CLK_BUFGP         |   0.000|
DI<10>      |   12.229(R)|   -7.566(R)|CLK_BUFGP         |   0.000|
DI<11>      |   12.236(R)|   -7.884(R)|CLK_BUFGP         |   0.000|
DI<12>      |   12.353(R)|   -8.157(R)|CLK_BUFGP         |   0.000|
DI<13>      |   11.486(R)|   -8.719(R)|CLK_BUFGP         |   0.000|
DI<14>      |   12.004(R)|   -9.237(R)|CLK_BUFGP         |   0.000|
DI<15>      |    6.849(R)|   -5.249(R)|CLK_BUFGP         |   0.000|
DI<1>       |   11.130(R)|   -5.383(R)|CLK_BUFGP         |   0.000|
DI<2>       |   10.058(R)|   -7.277(R)|CLK_BUFGP         |   0.000|
DI<3>       |   10.581(R)|   -7.690(R)|CLK_BUFGP         |   0.000|
DI<4>       |   10.475(R)|   -7.647(R)|CLK_BUFGP         |   0.000|
DI<5>       |   10.144(R)|   -7.142(R)|CLK_BUFGP         |   0.000|
DI<6>       |    9.560(R)|   -6.208(R)|CLK_BUFGP         |   0.000|
DI<7>       |   11.225(R)|   -5.518(R)|CLK_BUFGP         |   0.000|
DI<8>       |   11.963(R)|   -7.539(R)|CLK_BUFGP         |   0.000|
DI<9>       |   12.617(R)|   -8.317(R)|CLK_BUFGP         |   0.000|
EN          |    2.111(R)|   -0.818(R)|CLK_BUFGP         |   0.000|
MASK<0>     |   14.480(R)|   -7.357(R)|CLK_BUFGP         |   0.000|
MASK<1>     |   15.774(R)|   -7.965(R)|CLK_BUFGP         |   0.000|
MASK<2>     |   14.694(R)|   -6.159(R)|CLK_BUFGP         |   0.000|
MASK<3>     |    6.672(R)|   -5.104(R)|CLK_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock CLK to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
DO<0>       |    6.442(R)|CLK_BUFGP         |   0.000|
DO<1>       |    6.465(R)|CLK_BUFGP         |   0.000|
DO<2>       |    6.465(R)|CLK_BUFGP         |   0.000|
DO<3>       |    6.488(R)|CLK_BUFGP         |   0.000|
DO<4>       |    6.488(R)|CLK_BUFGP         |   0.000|
DO<5>       |    6.465(R)|CLK_BUFGP         |   0.000|
DO<6>       |    6.499(R)|CLK_BUFGP         |   0.000|
DO<7>       |    6.499(R)|CLK_BUFGP         |   0.000|
------------+------------+------------------+--------+

Analysis completed Mon Jan 09 12:05:17 2006
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Peak Memory Usage: 70 MB