main.vhd

这个是国外大学的项目代码

------------------------------------------------------------------------
--  main.vhd -- Main level
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
--  This is the main component level.
------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
    Port ( CLK      : in std_logic;
           --epp
           EPPASTB  : in std_logic;
           EPPDSTB  : in std_logic;
           EPPWRITE : in std_logic;
           EPPRST   : in std_logic;
           EPPWAIT  : out std_logic;
           EPPDB    : inout std_logic_vector(7 downto 0);
           --sram
           RAMDB    : inout std_logic_vector(7 downto 0);
           RAMADR   : out std_logic_vector(18 downto 0);
           RAMCS0   : out std_logic;
           RAMCS1   : out std_logic;
           RAMOE    : out std_logic;
           RAMWR    : out std_logic;
            --vga
           HS       : out std_logic;
           VS       : out std_logic;
           RED      : out std_logic;
           GRN      : out std_logic;
           BLU      : out std_logic;
            --dio4
           SEG      : out std_logic_vector(6 downto 0);
           AN       : out std_logic_vector(3 downto 0);
           LEDG     : out std_logic;
           LED      : out std_logic_vector(7 downto 0);
           SWT      : in std_logic_vector(7 downto 0);
           BTN      : in std_logic_vector(4 downto 0));
end main;   
architecture Behavioral of main is

component epp is
    Port ( CLK      : in std_logic;
           --epp
           EPPASTB  : in std_logic;
           EPPDSTB  : in std_logic;
           EPPWRITE : in std_logic;
           EPPRST   : in std_logic;
           EPPWAIT  : out std_logic;
           EPPDB    : inout std_logic_vector(7 downto 0);
           --memory
           EDI      : in std_logic_vector(7 downto 0);
           EDO      : out std_logic_vector(7 downto 0);
           EADR     : out std_logic_vector(19 downto 0);
           EOE      : out std_logic;
           EWR      : out std_logic;
           EBUSY    : out std_logic;
           --ctrl
           EIMGCH   : out std_logic;
           EIMGNR   : out std_logic_vector(3 downto 0);
           EPRCCH   : out std_logic;
           EPRCNR   : out std_logic_vector(2 downto 0);
           --vga
           HDELAY   : out std_logic_vector(2 downto 0);
           VDELAY   : out std_logic_vector(3 downto 0);
           PWMNR    : out std_logic_vector(2 downto 0);
           DSPMODE  : out std_logic_vector(1 downto 0));
end component;
    
component sram is
    Port ( CLK     : in std_logic;
           --sram
           RAMDB   : inout std_logic_vector(7 downto 0);
           RAMADR  : out std_logic_vector(18 downto 0);
           RAMCS0  : out std_logic;
           RAMCS1  : out std_logic;
           RAMOE   : out std_logic;
           RAMWR   : out std_logic;
           --general
           SDO     : out std_logic_vector(7 downto 0);
           --eppctrl
           EDO     : in std_logic_vector(7 downto 0);
           EADR    : in std_logic_vector(19 downto 0);
           EOE     : in std_logic;
           EWR     : in std_logic;
           EBUSY   : in std_logic;
           --ctrl
           CRD     : in std_logic;
           CADR    : in std_logic_vector(19 downto 0);
           --imgctrl
           ICRD    : in std_logic;
           ICADR   : in std_logic_vector(19 downto 0);
           --display
           IADR    : in std_logic_vector(19 downto 0);
           --prc
           PBUSY   : in std_logic;
           PRD     : in std_logic;
           PWR     : in std_logic;
           PDO     : in std_logic_vector(7 downto 0);
           PADR    : in std_logic_vector(19 downto 0));
end component;

component seg7 is
    Port ( CLK     : in std_logic;
           DATA    : in std_logic_vector(15 downto 0);
           SEG     : out std_logic_vector(6 downto 0);
           AN      : out std_logic_vector(3 downto 0));
end component;

component img is
    Port ( CLK   : in std_logic;
           --vga
           RED   : out std_logic;
           GRN   : out std_logic;
           BLU   : out std_logic;
           HS    : out std_logic;
           VS    : out std_logic;
           --epp 
           EBUSY : in std_logic;
           --data
           IDI   : in std_logic_vector(7 downto 0);
           IADR  : out std_logic_vector(19 downto 0);
           --ctrl
           SWT   : in std_logic_vector(7 downto 0);
           SADR  : in std_logic_vector(19 downto 0);
           IMGW  : in std_logic_vector(10 downto 0);
           IMGH  : in std_logic_vector(10 downto 0);
           --vga
           HDELAY   : in std_logic_vector(2 downto 0);
           VDELAY   : in std_logic_vector(3 downto 0);
           PWMNR    : in std_logic_vector(2 downto 0);
           DSPMODE  : in std_logic_vector(1 downto 0));
end component;

component imgctrl is
    Port ( CLK   : in std_logic;
           IMGNR : in std_logic_vector(3 downto 0);
           --sram
           ICRD  : out std_logic;
           ICDI  : in std_logic_vector(7 downto 0);
           ICADR : out std_logic_vector(19 downto 0);
           --ctrl
           SADR  : out std_logic_vector(19 downto 0);
           IMGW  : out std_logic_vector(10 downto 0);
           IMGH  : out std_logic_vector(10 downto 0));
end component;

component ctrl is
    Port ( CLK    : in std_logic;
           BTN    : in std_logic_vector(4 downto 0);
           --epp
           EBUSY  : in std_logic;
           EIMGCH : in std_logic;
           EIMGNR : in std_logic_vector(3 downto 0);
           EPRCCH : in std_logic;
           EPRCNR : in std_logic_vector(2 downto 0);
           --sram
           CRD    : out std_logic;
           CDI    : in std_logic_vector(7 downto 0);
           CADR   : out std_logic_vector(19 downto 0);
           --img
           IMGNR  : out std_logic_vector(3 downto 0);
           PRCDO  : out std_logic;
           PRCNR  : out std_logic_vector(2 downto 0);
           MAXIMG : out std_logic_vector(3 downto 0);
           MAXPRC : out std_logic_vector(2 downto 0);
           --prc
           PBUSY  : in std_logic);
end component;

component prc2 is
    Port ( CLK   : in std_logic;
           PRCDO : in std_logic;
           PRCNR : in std_logic_vector(2 downto 0);
           BUSY  : out std_logic;
           --sram
           RD    : out std_logic;
           WR    : out std_logic;
           DI    : in std_logic_vector(7 downto 0);
           DO    : out std_logic_vector(7 downto 0);
           ADR   : out std_logic_vector(19 downto 0));
end component;

--20 bit address wires
signal EADR, CADR, ICADR, IADR, SADR, PADR : 
    std_logic_vector(19 downto 0) := "00000000000000000000";
--signal wires
signal EBUSY, CRD, ICRD, EOE, EWR, 
    PRCDO, PBUSY, PRD, PWR, EPRCCH, EIMGCH: std_logic := '0';
signal DSPMODE : std_logic_vector(1 downto 0) := "00";
--8 bit data wires
signal SDO, EDO, PDO : std_logic_vector(7 downto 0) := "00000000";
--other internal wires
signal IMGW, IMGH : std_logic_vector(10 downto 0) := "00000000000";
signal PRCNR, EPRCNR, MAXPRC, PWMNR, HDELAY
    : std_logic_vector(2 downto 0) := "000";
signal IMGNR, EIMGNR, MAXIMG, VDELAY : std_logic_vector(3 downto 0) := "0000";
signal DATA : std_logic_vector(15 downto 0) := "0000000000000000";

begin
    
    epp0 : epp port map(
        CLK, EPPASTB, EPPDSTB, EPPWRITE, EPPRST, EPPWAIT, EPPDB, SDO, 
        EDO, EADR, EOE, EWR, EBUSY, EIMGCH, EIMGNR, EPRCCH, EPRCNR, 
        HDELAY, VDELAY, PWMNR, DSPMODE);
    seg70 : seg7 port map(
        CLK, DATA, SEG, AN);
    img0 : img port map(
        CLK, RED, GRN, BLU, HS, VS, EBUSY, SDO, IADR, SWT, 
        SADR, IMGW, IMGH, HDELAY, VDELAY, PWMNR, DSPMODE);
    sram0 : sram port map(
        CLK, RAMDB, RAMADR, RAMCS0, RAMCS1, RAMOE, RAMWR, 
        SDO, EDO, EADR, EOE, EWR, EBUSY, CRD, CADR, ICRD, ICADR, IADR, 
        PBUSY, PRD, PWR, PDO, PADR);
    ctrl0 : ctrl port map(
        CLK, BTN, EBUSY, EIMGCH, EIMGNR, EPRCCH, EPRCNR, 
        CRD, SDO, CADR, IMGNR, PRCDO, PRCNR, MAXIMG, MAXPRC, PBUSY);
    imgctrl0 : imgctrl port map(
        CLK, IMGNR, ICRD, SDO, ICADR, SADR, IMGW, IMGH);
    prc20 : prc2 port map(
        CLK, PRCDO, PRCNR, PBUSY, PRD, PWR, SDO, PDO, PADR);
    
    DATA <= IMGNR&MAXIMG&'0'&PRCNR&'0'&MAXPRC;
    LED <= EBUSY&PBUSY&DSPMODE&SWT(3 downto 0);
    LEDG <= not SWT(4);
end Behavioral;