📄 imgctrl2.vhd
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------------------------------------------------------------------------
-- imgctrl2.vhd -- Image header read control
------------------------------------------------------------------------
-- Author : Kovacs Laszlo - Attila
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
-- WebPack
------------------------------------------------------------------------
-- Reads the image header: the image width, height and
-- the starting address of the data.
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity imgctrl2 is
Port ( CLK : in std_logic;
EN : in std_logic;
DONE : out std_logic;
DI : in std_logic_vector(7 downto 0);
ADR : out std_logic_vector(2 downto 0);
IMGW : out std_logic_vector(10 downto 0);
IMGH : out std_logic_vector(10 downto 0);
IMGADR : out std_logic_vector(19 downto 0));
end imgctrl2;
architecture Behavioral of imgctrl2 is
signal iADR : std_logic_vector(3 downto 0) := "0000";
signal iIMGW, iIMGH : std_logic_vector(10 downto 0) := "00000000000";
signal iIMGADR : std_logic_vector(19 downto 0)
:= "00000000000000000000";
begin
DONE <= '1' when iADR = "1001" else '0';
ADR <= iADR(2 downto 0);
IMGW <= iIMGW;
IMGH <= iIMGH;
IMGADR <= iIMGADR;
process(CLK)
begin
if rising_edge(CLK) then
if EN = '0' then
iADR <= "0000";
elsif not(iADR = "1001") then
iADR <= iADR + 1;
end if;
end if;
end process;
process(CLK)
begin
if rising_edge(CLK) then
case iADR(3 downto 0) is
when "0010" =>
iIMGADR(19 downto 16) <= DI(3 downto 0);
when "0011" =>
iIMGADR(15 downto 8) <= DI;
when "0100" =>
iIMGADR(7 downto 0) <= DI;
when "0101" =>
iIMGW(10 downto 8) <= DI(2 downto 0);
when "0110" =>
iIMGW(7 downto 0) <= DI;
when "0111" =>
iIMGH(10 downto 8) <= DI(2 downto 0);
when "1000" =>
iIMGH(7 downto 0) <= DI;
when others =>
end case;
end if;
end process;
end Behavioral;
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