main.mrp

这个是国外大学的项目代码

Release 7.1.04i Map H.42
Xilinx Mapping Report File for Design 'main'

Design Information
------------------
Command Line   : C:/Program Files/Xilinx/bin/nt/map.exe -ise
e:\work\digilentinc\xiphard\XipHard.ise -intstyle ise -p xc2s200e-pq208-6 -cm
area -pr b -k 4 -c 100 -tx off -o main_map.ncd main.ngd main.pcf 
Target Device  : xc2s200e
Target Package : pq208
Target Speed   : -6
Mapper Version : spartan2e -- $Revision: 1.26.6.4 $
Mapped Date    : Sat Jan 14 01:47:39 2006

Design Summary
--------------
Number of errors:      0
Number of warnings:    4
Logic Utilization:
  Number of Slice Flip Flops:     1,359 out of  4,704   28%
  Number of 4 input LUTs:         2,061 out of  4,704   43%
Logic Distribution:
    Number of occupied Slices:                       1,486 out of  2,352   63%
    Number of Slices containing only related logic:  1,486 out of  1,486  100%
    Number of Slices containing unrelated logic:         0 out of  1,486    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        2,287 out of  4,704   48%
      Number used as logic:                     2,061
      Number used as a route-thru:                223
      Number used as Shift registers:               3
   Number of bonded IOBs:            82 out of    142   57%
      IOB Flip Flops:                              55
   Number of Block RAMs:              9 out of     14   64%
   Number of GCLKs:                   3 out of      4   75%
   Number of GCLKIOBs:                1 out of      4   25%
   Number of DLLs:                    1 out of      4   25%

Total equivalent gate count for design:  183,033
Additional JTAG gate count for IOBs:  3,984
Peak Memory Usage:  122 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFG symbol
   "img0/clkgen0/clk2xbuf" (output signal=img0/CLK2X) has a mix of clock and
   non-clock loads. Some of the non-clock loads are (maximum of 5 listed):
   Pin I2 of img0/pixel0/pwm2red/DI<5>120
   Pin I1 of img0/pixel0/pwm2blu/DI<4>_rn_3111_G
   Pin I1 of img0/pixel0/pwm2red/DI<4>_rn_3111_G
   Pin I3 of img0/pixel0/pwmmd2xred/pwmsel<0>1_SW0
   Pin I0 of img0/pixel0/pwmmd2xred/pwmsel<0>_SW0
WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFG symbol
   "img0/clkgen0/iCLK2_BUFG" (output signal=img0/clkgen0/iCLK2) has a mix of
   clock and non-clock loads. Some of the non-clock loads are (maximum of 5
   listed):
   Pin I1 of img0/pixel0/pwm2red/DI<5>120
   Pin I2 of img0/pixel0/pwmmd2xred/_n00151
   Pin I1 of img0/pixel0/pwm2xred/_n00042
   Pin CLR of img0/clkgen0/iCLK2
   Pin I2 of img0/pixel0/pwm2xred/_n00051
WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFG symbol
   "img0/clkgen0/iCLK4_BUFG" (output signal=img0/clkgen0/iCLK4) has a mix of
   clock and non-clock loads. Some of the non-clock loads are (maximum of 5
   listed):
   Pin I1 of img0/pixel0/pwmmd2xred/_n00151
   Pin CLR of img0/clkgen0/iCLK4
   Pin I0 of img0/pixel0/pwm2xred/_n00051
   Pin I3 of img0/pixel0/pwmeqred/DI<4>6
   Pin I3 of img0/pixel0/pwmeqgrn/DI<4>6
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
   	ctrl0/iIMGNR_inst_cy_12
   	ctrl0/iIMGNR_inst_cy_13

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------
   1 block(s) removed
  11 block(s) optimized away

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

Loadless block "img0/clkgen0/clkinbuf" (CKBUF) removed.

Optimized Block(s):
TYPE 		BLOCK
LUT1 		N1_rt
LUT1 		N1_rt1
LUT1 		N1_rt2
LUT1 		N1_rt3
LUT1 		N1_rt4
LUT1 		N1_rt5
LUT1 		N1_rt6
LUT1 		N1_rt7
LUT1 		N1_rt8
GND 		XST_GND
VCC 		XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| CLK                                | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       |
| AN<0>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| AN<1>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| AN<2>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |