📄 pwm2xeq.vhd
字号:
------------------------------------------------------------------------
-- pwm2xeq.vhd -- Pulse Width Modulator
------------------------------------------------------------------------
-- Author : Kovacs Laszlo - Attila
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
-- WebPack
------------------------------------------------------------------------
-- This Pulse Width Modulator according to the 4 most significant bits
-- of the data input selects one of the 16 logics (pulse widths),
-- using inverse clock signals, so the pulse modulations does
-- not have the same length.
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pwm2xeq is
Port ( CLK2X : in std_logic;
CLK : in std_logic;
CLK2 : in std_logic;
CLK4 : in std_logic;
DO : out std_logic;
DI : in std_logic_vector(7 downto 0));
end pwm2xeq;
architecture Behavioral of pwm2xeq is
begin
with DI(7 downto 4) select
DO <= '1' when "1111", --16
CLK2X or CLK or CLK2 or CLK4 when "1110", --15
CLK2X or CLK or CLK2 when "1101", --14
CLK2X or CLK or (CLK2 and CLK4) when "1100", --13
CLK2X or CLK when "1011", --12
CLK2X or (CLK and (CLK2 or CLK4)) when "1010", --11
CLK2X or (CLK and CLK2) when "1001", --10
CLK2X or (CLK and CLK2 and CLK4) when "1000", --09
CLK2X when "0111", --08
CLK2X and (CLK or CLK2 or CLK4) when "0110", --07
CLK2X and (CLK or CLK2) when "0101", --06
CLK2X and (CLK or (CLK2 and CLK4)) when "0100", --05
CLK2X and CLK when "0011", --04
CLK2X and CLK and (CLK2 or CLK4) when "0010", --03
CLK2X and CLK and CLK2 when "0001", --02
'0' when others;
end Behavioral;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -