prc2.syr

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Synthesizing Unit <creg>.
    Related source file is "E:/work/digilentinc/XipHard/creg.vhd".
    Found 8-bit register for signal <iDO>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <creg> synthesized.


Synthesizing Unit <clog>.
    Related source file is "E:/work/digilentinc/XipHard/clog.vhd".
Unit <clog> synthesized.


Synthesizing Unit <cfifo>.
    Related source file is "E:/work/digilentinc/XipHard/cfifo.vhd".
    Found 9-bit up counter for signal <rdaddr>.
    Found 9-bit updown counter for signal <size>.
    Found 9-bit up counter for signal <wraddr>.
    Summary:
	inferred   3 Counter(s).
Unit <cfifo> synthesized.


Synthesizing Unit <conv>.
    Related source file is "E:/work/digilentinc/XipHard/conv.vhd".
    Found 12-bit shift register for signal <valid<11>>.
    Summary:
	inferred   1 Shift register(s).
Unit <conv> synthesized.


Synthesizing Unit <imgctrl2>.
    Related source file is "E:/work/digilentinc/XipHard/imgctrl2.vhd".
    Found 4-bit up counter for signal <iADR>.
    Found 20-bit register for signal <iIMGADR>.
    Found 11-bit register for signal <iIMGH>.
    Found 11-bit register for signal <iIMGW>.
    Summary:
	inferred   1 Counter(s).
	inferred  42 D-type flip-flop(s).
Unit <imgctrl2> synthesized.


Synthesizing Unit <prcctrl>.
    Related source file is "E:/work/digilentinc/XipHard/prcctrl.vhd".
    Found 4-bit up counter for signal <iADR>.
    Found 4-bit register for signal <iIMGDEST>.
    Found 4-bit register for signal <iIMGSRC>.
    Found 8-bit register for signal <iMASK0>.
    Found 8-bit register for signal <iMASK1>.
    Found 8-bit register for signal <iMASK2>.
    Found 8-bit register for signal <iMASK3>.
    Found 8-bit register for signal <iMASK4>.
    Found 8-bit register for signal <iMASK5>.
    Found 8-bit register for signal <iMASK6>.
    Found 8-bit register for signal <iMASK7>.
    Found 8-bit register for signal <iMASK8>.
    Found 8-bit register for signal <iMASK9>.
    Summary:
	inferred   1 Counter(s).
	inferred  88 D-type flip-flop(s).
Unit <prcctrl> synthesized.


Synthesizing Unit <prc2>.
    Related source file is "E:/work/digilentinc/XipHard/prc2.vhd".
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 11                                             |
    | Transitions        | 24                                             |
    | Inputs             | 11                                             |
    | Outputs            | 11                                             |
    | Clock              | CLK (rising_edge)                              |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 3-bit subtractor for signal <$n0000> created at line 134.
    Found 20-bit adder for signal <$n0036>.
    Found 20-bit adder for signal <$n0037>.
    Found 11-bit adder for signal <$n0043> created at line 238.
    Found 11-bit comparator equal for signal <$n0045> created at line 237.
    Found 11-bit comparator equal for signal <$n0047> created at line 238.
    Found 11-bit comparator equal for signal <$n0048> created at line 213.
    Found 2-bit up counter for signal <CCOLOR>.
    Found 20-bit register for signal <CDESTADR>.
    Found 11-bit up counter for signal <CHEIGHT>.
    Found 20-bit register for signal <CSRCADR>.
    Found 11-bit up counter for signal <CWIDTH>.
    Found 1-bit register for signal <iBUSY>.
    Found 3-bit register for signal <iPRCNR>.
    Found 1-bit register for signal <iPRCSTART>.
    Found 1-bit register for signal <iPROCESS>.
    Found 1-bit register for signal <iRDBUFF>.
    Found 1-bit register for signal <iRDDATA>.
    Found 1-bit register for signal <iRDDEST>.
    Found 1-bit register for signal <iRDEND>.
    Found 1-bit register for signal <iRDPRC>.
    Found 1-bit register for signal <iRDSRC>.
    Found 1-bit register for signal <iRDSTART>.
    Found 1-bit register for signal <iWRDATA>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   3 Counter(s).
	inferred  54 D-type flip-flop(s).
	inferred   4 Adder/Subtractor(s).
	inferred   3 Comparator(s).
Unit <prc2> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <state[1:11]> with one-hot encoding.
----------------------------
 State       | Encoding
----------------------------
 idle        | 00000000001
 rdprc       | 00000000010
 rdsrc       | 00000000100
 rddest      | 00000001000
 prcstart    | 00000010000
 rdstart     | 00000100000
 rddata      | 00001000000
 rdend       | 00010000000
 wrdatastart | 00100000000
 wrdata      | 01000000000
 wrdataend   | 10000000000
----------------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Adders/Subtractors               : 21
 11-bit adder                      : 1
 16-bit adder                      : 17
 20-bit adder                      : 2
 3-bit subtractor                  : 1
# Counters                         : 13
 11-bit up counter                 : 6
 2-bit up counter                  : 1
 4-bit up counter                  : 3
 9-bit up counter                  : 2
 9-bit updown counter              : 1
# Registers                        : 163
 1-bit register                    : 106
 11-bit register                   : 2
 16-bit register                   : 30
 2-bit register                    : 2
 20-bit register                   : 2
 3-bit register                    : 1
 4-bit register                    : 2
 8-bit register                    : 18
# Shift Registers                  : 1
 12-bit shift register             : 1
# Comparators                      : 5
 11-bit comparator equal           : 3
 11-bit comparator not equal       : 2
# Multiplexers                     : 3
 8-bit 4-to-1 multiplexer          : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1293 - FF/Latch  <iDO_15> has a constant value of 0 in block <cmul>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <iDO_13> has a constant value of 0 in block <cmul>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <iDO_14> has a constant value of 0 in block <cmul>.
WARNING:Xst:1291 - FF/Latch <iIMGH_5> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGW_10> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGH_4> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGH_3> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGH_2> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGH_1> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGH_6> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGH_7> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGH_8> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGH_9> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGH_10> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGW_0> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGW_1> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGW_2> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGW_3> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGW_4> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGW_5> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGW_6> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGW_7> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGW_8> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGW_9> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <iIMGH_0> is unconnected in block <sRDDEST>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGH_5> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGW_10> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGH_4> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGH_3> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGH_2> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGH_1> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGH_6> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGH_7> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGH_8> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGH_9> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGH_10> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGW_0> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGW_1> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGW_2> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGW_3> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGW_4> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGW_5> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGW_6> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGW_7> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGW_8> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGW_9> is unconnected in block <prc2>.
WARNING:Xst:1291 - FF/Latch <sRDDEST/iIMGH_0> is unconnected in block <prc2>.

Optimizing unit <prc2> ...

Optimizing unit <cmul> ...

Optimizing unit <clog> ...

Optimizing unit <conv> ...

Optimizing unit <cbuff> ...

Optimizing unit <cfifo> ...

Optimizing unit <cround> ...

Optimizing unit <prcctrl> ...

Optimizing unit <c2comp> ...

Optimizing unit <cdiv> ...
Loading device for application Rf_Device from file '2s200e.nph' in environment C:/Program Files/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block prc2, actual ratio is 30.