img320.syr

这个是国外大学的项目代码

Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 116

Macro Statistics :
# Registers                        : 10
#      20-bit register             : 1
#      8-bit register              : 9
# Counters                         : 2
#      20-bit up counter           : 2
# Shift Registers                  : 1
#      8-bit shift register        : 1
# Multiplexers                     : 3
#      8-bit 4-to-1 multiplexer    : 3
# Comparators                      : 4
#      11-bit comparator less      : 2
#      9-bit comparator less       : 2

Cell Usage :
# BELS                             : 265
#      GND                         : 1
#      INV                         : 2
#      LUT1                        : 4
#      LUT2                        : 21
#      LUT3                        : 12
#      LUT3_L                      : 84
#      LUT4                        : 7
#      LUT4_L                      : 24
#      MUXCY                       : 69
#      VCC                         : 1
#      XORCY                       : 40
# FlipFlops/Latches                : 133
#      FDE                         : 109
#      FDR                         : 24
# Shifters                         : 1
#      SRL16E                      : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 115
#      IBUF                        : 71
#      OBUF                        : 44
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200epq208-6 

 Number of Slices:                     106  out of   2352     4%  
 Number of Slice Flip Flops:           133  out of   4704     2%  
 Number of 4 input LUTs:               153  out of   4704     3%  
 Number of bonded IOBs:                116  out of    146    79%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 134   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.541ns (Maximum Frequency: 180.473MHz)
   Minimum input arrival time before clock: 14.600ns
   Maximum output required time after clock: 6.744ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
  Clock period: 5.541ns (frequency: 180.473MHz)
  Total number of paths / destination ports: 557 / 109
-------------------------------------------------------------------------
Delay:               5.541ns (Levels of Logic = 21)
  Source:            eadr_0 (FF)
  Destination:       eadr_19 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: eadr_0 to eadr_19
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.992   1.150  eadr_0 (eadr_0)
     LUT3_L:I2->LO         1   0.468   0.000  eadr_inst_lut3_01 (eadr_inst_lut3_0)
     MUXCY:S->O            1   0.515   0.000  eadr_inst_cy_1 (eadr_inst_cy_1)
     MUXCY:CI->O           1   0.058   0.000  eadr_inst_cy_2 (eadr_inst_cy_2)
     MUXCY:CI->O           1   0.058   0.000  eadr_inst_cy_3 (eadr_inst_cy_3)
     MUXCY:CI->O           1   0.058   0.000  eadr_inst_cy_4 (eadr_inst_cy_4)
     MUXCY:CI->O           1   0.058   0.000  eadr_inst_cy_5 (eadr_inst_cy_5)
     MUXCY:CI->O           1   0.058   0.000  eadr_inst_cy_6 (eadr_inst_cy_6)
     MUXCY:CI->O           1   0.058   0.000  eadr_inst_cy_7 (eadr_inst_cy_7)
     MUXCY:CI->O           1   0.058   0.000  eadr_inst_cy_8 (eadr_inst_cy_8)
     MUXCY:CI->O           1   0.058   0.000  eadr_inst_cy_9 (eadr_inst_cy_9)
     MUXCY:CI->O           1   0.058   0.000  eadr_inst_cy_10 (eadr_inst_cy_10)
     MUXCY:CI->O           1   0.058   0.000  eadr_inst_cy_11 (eadr_inst_cy_11)
     MUXCY:CI->O           1   0.058   0.000  eadr_inst_cy_12 (eadr_inst_cy_12)
     MUXCY:CI->O           1   0.058   0.000  eadr_inst_cy_13 (eadr_inst_cy_13)
     MUXCY:CI->O           1   0.058   0.000  eadr_inst_cy_14 (eadr_inst_cy_14)
     MUXCY:CI->O           1   0.058   0.000  eadr_inst_cy_15 (eadr_inst_cy_15)
     MUXCY:CI->O           1   0.058   0.000  eadr_inst_cy_16 (eadr_inst_cy_16)
     MUXCY:CI->O           1   0.058   0.000  eadr_inst_cy_17 (eadr_inst_cy_17)
     MUXCY:CI->O           1   0.058   0.000  eadr_inst_cy_18 (eadr_inst_cy_18)
     MUXCY:CI->O           0   0.058   0.000  eadr_inst_cy_19 (eadr_inst_cy_19)
     XORCY:CI->O           1   0.648   0.000  eadr_inst_sum_19 (eadr_inst_sum_19)
     FDE:D                     0.724          eadr_19
    ----------------------------------------
    Total                      5.541ns (4.391ns logic, 1.150ns route)
                                       (79.2% logic, 20.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
  Total number of paths / destination ports: 44374 / 265
-------------------------------------------------------------------------
Offset:              14.600ns (Levels of Logic = 14)
  Source:            VGAHC<2> (PAD)
  Destination:       eadr_17 (FF)
  Destination Clock: CLK rising

  Data Path: VGAHC<2> to eadr_17
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            31   0.797   3.275  VGAHC_2_IBUF (VGAHC_2_IBUF)
     LUT2:I0->O            1   0.468   0.000  XNor_stagelut (N11)
     MUXCY:S->O            1   0.515   0.000  XNor_stagecy (XNor_stage_cyo)
     MUXCY:CI->O           1   0.058   0.000  XNor_stagecy_rn_0 (XNor_stage_cyo1)
     MUXCY:CI->O           1   0.058   0.000  XNor_stagecy_rn_1 (XNor_stage_cyo2)
     MUXCY:CI->O           1   0.058   0.000  XNor_stagecy_rn_2 (XNor_stage_cyo3)
     MUXCY:CI->O           1   0.058   0.000  XNor_stagecy_rn_3 (XNor_stage_cyo4)
     MUXCY:CI->O           1   0.058   0.000  XNor_stagecy_rn_4 (XNor_stage_cyo5)
     MUXCY:CI->O           1   0.058   0.000  XNor_stagecy_rn_5 (XNor_stage_cyo6)
     MUXCY:CI->O           1   0.058   0.000  XNor_stagecy_rn_6 (XNor_stage_cyo7)
     MUXCY:CI->O           3   0.058   1.320  XNor_stagecy_rn_7 (XNor_stage_cyo8)
     LUT2:I0->O            4   0.468   1.520  _n00171 (hin)
     LUT4:I1->O            2   0.468   1.150  Ker01 (N01)
     LUT4:I1->O           20   0.468   3.000  _n00371 (_n0037)
     FDE:CE                    0.687          oadr_0
    ----------------------------------------
    Total                     14.600ns (4.335ns logic, 10.265ns route)
                                       (29.7% logic, 70.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
  Total number of paths / destination ports: 44 / 44
-------------------------------------------------------------------------
Offset:              6.744ns (Levels of Logic = 1)
  Source:            DBLU_7 (FF)
  Destination:       DBLU<7> (PAD)
  Source Clock:      CLK rising

  Data Path: DBLU_7 to DBLU<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.992   1.150  DBLU_7 (DBLU_7)
     OBUF:I->O                 4.602          DBLU_7_OBUF (DBLU<7>)
    ----------------------------------------
    Total                      6.744ns (5.594ns logic, 1.150ns route)
                                       (82.9% logic, 17.1% route)

=========================================================================
CPU : 7.06 / 7.45 s | Elapsed : 7.00 / 8.00 s
 
--> 

Total memory usage is 89800 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)