main.syr

这个是国外大学的项目代码

Selected Device : 2s200epq208-6 

 Number of Slices:                    1275  out of   2352    54%  
 Number of Slice Flip Flops:          1414  out of   4704    30%  
 Number of 4 input LUTs:              2145  out of   4704    45%  
 Number of bonded IOBs:                 83  out of    146    56%  
 Number of BRAMs:                        9  out of     14    64%  
 Number of GCLKs:                        4  out of      4   100%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | IBUFG                  | 1424  |
img0/clkgen0/iCLK4:Q               | BUFG                   | 1     |
img0/clkgen0/iCLK2:Q               | BUFG                   | 1     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 14.224ns (Maximum Frequency: 70.304MHz)
   Minimum input arrival time before clock: 9.916ns
   Maximum output required time after clock: 36.704ns
   Maximum combinational path delay: 37.970ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
  Clock period: 14.224ns (frequency: 70.304MHz)
  Total number of paths / destination ports: 96027 / 2966
-------------------------------------------------------------------------
Delay:               14.224ns (Levels of Logic = 11)
  Source:            img0/vga0/ivc_9 (FF)
  Destination:       img0/vga0/ivc_8 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: img0/vga0/ivc_9 to img0/vga0/ivc_8
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             7   0.992   1.950  img0/vga0/ivc_9 (img0/vga0/ivc_9)
     LUT4:I2->O            2   0.468   1.150  img0/vga0/_n000619 (CHOICE3354)
     LUT4:I3->O            4   0.468   1.520  img0/vga0/_n000628 (img0/vga0/_n0006)
     LUT3:I0->O            1   0.468   0.920  img0/vga0/hcount<0>1 (img0/vga0/hcount<0>)
     LUT4_L:I1->LO         1   0.468   0.000  img0/vga0/Eq_stagelut (img0/vga0/N7)
     MUXCY:S->O            1   0.515   0.000  img0/vga0/Eq_stagecy (img0/vga0/Eq_stage_cyo)
     MUXCY:CI->O           1   0.058   0.000  img0/vga0/Eq_stagecy_rn_0 (img0/vga0/Eq_stage_cyo1)
     MUXCY:CI->O           1   0.058   0.000  img0/vga0/Eq_stagecy_rn_1 (img0/vga0/Eq_stage_cyo2)
     MUXCY:CI->O           1   0.058   0.000  img0/vga0/Eq_stagecy_rn_2 (img0/vga0/Eq_stage_cyo3)
     MUXCY:CI->O           1   0.058   0.000  img0/vga0/Eq_stagecy_rn_3 (img0/vga0/Eq_stage_cyo4)
     MUXCY:CI->O           4   0.058   1.520  img0/vga0/Eq_stagecy_rn_4 (img0/vga0/_n0011)
     LUT3:I0->O           12   0.468   2.450  img0/vga0/_n000247 (img0/vga0/_n0002)
     FDRE:R                    0.577          img0/vga0/ivc_0
    ----------------------------------------
    Total                     14.224ns (4.714ns logic, 9.510ns route)
                                       (33.1% logic, 66.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'img0/clkgen0/iCLK4:Q'
  Clock period: 5.869ns (frequency: 170.387MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               5.869ns (Levels of Logic = 0)
  Source:            img0/clkgen0/iCLK8 (FF)
  Destination:       img0/clkgen0/iCLK8 (FF)
  Source Clock:      img0/clkgen0/iCLK4:Q rising
  Destination Clock: img0/clkgen0/iCLK4:Q rising

  Data Path: img0/clkgen0/iCLK8 to img0/clkgen0/iCLK8
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             72   0.992   4.300  img0/clkgen0/iCLK8 (img0/clkgen0/iCLK8)
     FDR:R                     0.577          img0/clkgen0/iCLK8
    ----------------------------------------
    Total                      5.869ns (1.569ns logic, 4.300ns route)
                                       (26.7% logic, 73.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'img0/clkgen0/iCLK2:Q'
  Clock period: 8.464ns (frequency: 118.147MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               8.464ns (Levels of Logic = 1)
  Source:            img0/clkgen0/iCLK4 (FF)
  Destination:       img0/clkgen0/iCLK4 (FF)
  Source Clock:      img0/clkgen0/iCLK2:Q rising
  Destination Clock: img0/clkgen0/iCLK2:Q rising

  Data Path: img0/clkgen0/iCLK4 to img0/clkgen0/iCLK4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.992   0.920  img0/clkgen0/iCLK4 (img0/clkgen0/iCLK41)
     BUFG:I->O           119   0.500   5.475  img0/clkgen0/iCLK4_BUFG (img0/clkgen0/iCLK4)
     FDR:R                     0.577          img0/clkgen0/iCLK4
    ----------------------------------------
    Total                      8.464ns (2.069ns logic, 6.395ns route)
                                       (24.4% logic, 75.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
  Total number of paths / destination ports: 277 / 149
-------------------------------------------------------------------------
Offset:              9.916ns (Levels of Logic = 5)
  Source:            EPPDSTB (PAD)
  Destination:       epp0/iHDELAY_2 (FF)
  Destination Clock: CLK rising

  Data Path: EPPDSTB to epp0/iHDELAY_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.797   1.150  EPPDSTB_IBUF (EPPDSTB_IBUF)
     LUT3_D:I2->O         10   0.468   2.250  epp0/_n00231 (epp0/DATAOP)
     LUT3_D:I0->O          1   0.468   0.920  Ker711 (N71)
     LUT3_D:I0->O          1   0.468   0.920  Ker731 (N73)
     LUT3:I0->O            3   0.468   1.320  epp0/_n00511 (epp0/_n0051)
     FDE:CE                    0.687          epp0/iHDELAY_0
    ----------------------------------------
    Total                      9.916ns (3.356ns logic, 6.560ns route)
                                       (33.8% logic, 66.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
  Total number of paths / destination ports: 27103 / 60
-------------------------------------------------------------------------
Offset:              36.704ns (Levels of Logic = 20)
  Source:            epp0/idADR_3 (FF)
  Destination:       BLU (PAD)
  Source Clock:      CLK rising

  Data Path: epp0/idADR_3 to BLU
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              4   0.992   1.520  epp0/idADR_3 (epp0/idADR_3)
     LUT3:I0->O            2   0.468   1.150  Ker721 (N72)
     LUT3_L:I2->LO         1   0.468   0.100  epp0/_n0026_SW0 (N1313)
     LUT4_D:I3->O         18   0.468   2.900  epp0/_n0026 (epp0/_n0026)
     LUT2:I1->O           22   0.468   3.050  epp0/_n00241 (LED_7_OBUF)
     LUT4:I2->O            5   0.468   1.720  img0/DBLU<7>26 (CHOICE1708)
     LUT3:I0->O           31   0.468   3.275  img0/DBLU<7>34 (img0/DBLU<7>)
     LUT4:I0->O            5   0.468   1.720  img0/pixel0/pwmmd2xblu/pwmsel2<4>1 (img0/pixel0/pwmmd2xblu/pwmsel2<4>)
     LUT4:I0->O            1   0.468   0.000  img0/pixel0/pwmmd2xblu/Mrom_pwmsel3_inst_mux_f5_0111_F (N6020)
     MUXF5:I0->O          11   0.422   2.350  img0/pixel0/pwmmd2xblu/Mrom_pwmsel3_inst_mux_f5_0111 (img0/pixel0/pwmmd2xblu/pwmsel3<0>)
     LUT4:I0->O            4   0.468   1.520  img0/pixel0/pwmmd2xblu/pwmsel<0>1_SW0 (N5655)
     LUT4:I2->O            1   0.468   0.000  img0/pixel0/pwmmd2xblu/pwmsel<0>15 (img0/pixel0/pwmmd2xblu/MUX_BLOCK_N16)
     MUXF5:I0->O           1   0.422   0.000  img0/pixel0/pwmmd2xblu/pwmsel<1>_rn_6 (img0/pixel0/pwmmd2xblu/MUX_BLOCK_pwmsel<1>_MUXF57)
     MUXF6:I0->O           1   0.220   0.920  img0/pixel0/pwmmd2xblu/pwmsel<2>_rn_2 (img0/pixel0/pwmmd2xblu/MUX_BLOCK_pwmsel<2>_MUXF63)
     LUT3:I1->O            1   0.468   0.000  img0/pixel0/pwmmd2xblu/Mmux_DO_DO111_F (N5966)
     MUXF5:I0->O           1   0.422   0.920  img0/pixel0/pwmmd2xblu/Mmux_DO_DO111 (img0/pixel0/bmd2x)
     LUT3:I1->O            1   0.468   0.000  img0/pixel0/PWMNR<0>1 (img0/pixel0/MUX_BLOCK_N3)
     MUXF5:I0->O           1   0.422   0.000  img0/pixel0/PWMNR<1> (img0/pixel0/MUX_BLOCK_PWMNR<1>_MUXF5)
     MUXF6:I1->O           1   0.133   0.920  img0/pixel0/Mmux_BLU_BLU (img0/VBLU)
     LUT2:I0->O            1   0.468   0.920  img0/BLU1 (BLU_OBUF)
     OBUF:I->O                 4.602          BLU_OBUF (BLU)
    ----------------------------------------
    Total                     36.704ns (13.719ns logic, 22.985ns route)
                                       (37.4% logic, 62.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'img0/clkgen0/iCLK2:Q'
  Total number of paths / destination ports: 333 / 3
-------------------------------------------------------------------------
Offset:              24.509ns (Levels of Logic = 13)
  Source:            img0/clkgen0/iCLK4 (FF)
  Destination:       GRN (PAD)
  Source Clock:      img0/clkgen0/iCLK2:Q rising

  Data Path: img0/clkgen0/iCLK4 to GRN
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.992   0.920  img0/clkgen0/iCLK4 (img0/clkgen0/iCLK41)
     BUFG:I->O           119   0.500   5.475  img0/clkgen0/iCLK4_BUFG (img0/clkgen0/iCLK4)
     LUT2:I0->O            9   0.468   2.150  img0/pixel0/pwm2blu/_n00171 (img0/pixel0/pwm2blu/N40)
     LUT4:I0->O            6   0.468   1.850  img0/pixel0/pwm2xblu/_n00252 (img0/pixel0/pwm2xblu/_n0051<4>)
     LUT3:I1->O            1   0.468   0.000  img0/pixel0/pwm2xblu/DI<3>9 (img0/pixel0/pwm2xblu/MUX_BLOCK_N10)
     MUXF5:I0->O           1   0.422   0.000  img0/pixel0/pwm2xblu/DI<4>_rn_3 (img0/pixel0/pwm2xblu/MUX_BLOCK_DI<4>_MUXF54)
     MUXF6:I1->O           1   0.133   0.920  img0/pixel0/pwm2xblu/DI<5>_rn_1 (img0/pixel0/pwm2xblu/MUX_BLOCK_DI<5>_MUXF62)
     LUT3:I1->O            1   0.468   0.000  img0/pixel0/pwm2xblu/Mmux_DO_DO111_F (N5886)
     MUXF5:I0->O           1   0.422   0.920  img0/pixel0/pwm2xblu/Mmux_DO_DO111 (img0/pixel0/b2x)
     LUT3:I2->O            1   0.468   0.000  img0/pixel0/PWMNR<0>1 (img0/pixel0/MUX_BLOCK_N3)
     MUXF5:I0->O           1   0.422   0.000  img0/pixel0/PWMNR<1> (img0/pixel0/MUX_BLOCK_PWMNR<1>_MUXF5)
     MUXF6:I1->O           1   0.133   0.920  img0/pixel0/Mmux_BLU_BLU (img0/VBLU)
     LUT2:I0->O            1   0.468   0.920  img0/BLU1 (BLU_OBUF)
     OBUF:I->O                 4.602          BLU_OBUF (BLU)
    ----------------------------------------
    Total                     24.509ns (10.434ns logic, 14.075ns route)
                                       (42.6% logic, 57.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'img0/clkgen0/iCLK4:Q'
  Total number of paths / destination ports: 186 / 3
-------------------------------------------------------------------------
Offset:              21.914ns (Levels of Logic = 12)
  Source:            img0/clkgen0/iCLK8 (FF)
  Destination:       GRN (PAD)
  Source Clock:      img0/clkgen0/iCLK4:Q rising

  Data Path: img0/clkgen0/iCLK8 to GRN
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             72   0.992   4.300  img0/clkgen0/iCLK8 (img0/clkgen0/iCLK8)
     LUT2:I1->O            9   0.468   2.150  img0/pixel0/pwm2blu/_n00171 (img0/pixel0/pwm2blu/N40)
     LUT4:I0->O            6   0.468   1.850  img0/pixel0/pwm2xblu/_n00252 (img0/pixel0/pwm2xblu/_n0051<4>)
     LUT3:I1->O            1   0.468   0.000  img0/pixel0/pwm2xblu/DI<3>9 (img0/pixel0/pwm2xblu/MUX_BLOCK_N10)
     MUXF5:I0->O           1   0.422   0.000  img0/pixel0/pwm2xblu/DI<4>_rn_3 (img0/pixel0/pwm2xblu/MUX_BLOCK_DI<4>_MUXF54)
     MUXF6:I1->O           1   0.133   0.920  img0/pixel0/pwm2xblu/DI<5>_rn_1 (img0/pixel0/pwm2xblu/MUX_BLOCK_DI<5>_MUXF62)
     LUT3:I1->O            1   0.468   0.000  img0/pixel0/pwm2xblu/Mmux_DO_DO111_F (N5886)
     MUXF5:I0->O           1   0.422   0.920  img0/pixel0/pwm2xblu/Mmux_DO_DO111 (img0/pixel0/b2x)
     LUT3:I2->O            1   0.468   0.000  img0/pixel0/PWMNR<0>1 (img0/pixel0/MUX_BLOCK_N3)
     MUXF5:I0->O           1   0.422   0.000  img0/pixel0/PWMNR<1> (img0/pixel0/MUX_BLOCK_PWMNR<1>_MUXF5)
     MUXF6:I1->O           1   0.133   0.920  img0/pixel0/Mmux_BLU_BLU (img0/VBLU)
     LUT2:I0->O            1   0.468   0.920  img0/BLU1 (BLU_OBUF)
     OBUF:I->O                 4.602          BLU_OBUF (BLU)
    ----------------------------------------
    Total                     21.914ns (9.934ns logic, 11.980ns route)
                                       (45.3% logic, 54.7% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 8026 / 16
-------------------------------------------------------------------------
Delay:               37.970ns (Levels of Logic = 13)
  Source:            CLK (PAD)
  Destination:       GRN (PAD)

  Data Path: CLK to GRN
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUFG:I->O         1548   1.297  20.700  CLK_IBUFG (CLK_IBUFG)
     LUT2:I1->O            4   0.468   1.520  img0/pixel0/pwmmd2xred/_n00151_SW0 (N5054)
     LUT4:I3->O            6   0.468   1.850  img0/pixel0/pwmmd2xred/_n00151 (img0/pixel0/pwmmd2xred/_n0051<14>)
     LUT4:I2->O            1   0.468   0.000  img0/pixel0/pwmmd2xred/pwmsel<0>12 (img0/pixel0/pwmmd2xred/MUX_BLOCK_N13)
     MUXF5:I1->O           1   0.403   0.000  img0/pixel0/pwmmd2xred/pwmsel<1>_rn_5 (img0/pixel0/pwmmd2xred/MUX_BLOCK_pwmsel<1>_MUXF56)
     MUXF6:I1->O           1   0.133   0.920  img0/pixel0/pwmmd2xred/pwmsel<2>_rn_2 (img0/pixel0/pwmmd2xred/MUX_BLOCK_pwmsel<2>_MUXF63)
     LUT3:I1->O            1   0.468   0.000  img0/pixel0/pwmmd2xred/Mmux_DO_DO111_F (N5990)
     MUXF5:I0->O           1   0.422   0.920  img0/pixel0/pwmmd2xred/Mmux_DO_DO111 (img0/pixel0/rmd2x)
     LUT3:I1->O            1   0.468   0.000  img0/pixel0/PWMNR<0>9 (img0/pixel0/MUX_BLOCK_N11)
     MUXF5:I0->O           1   0.422   0.000  img0/pixel0/PWMNR<1>_rn_3 (img0/pixel0/MUX_BLOCK_PWMNR<1>_MUXF54)
     MUXF6:I1->O           1   0.133   0.920  img0/pixel0/Mmux_BLU_BLU_BLU_rn_0 (img0/VRED)
     LUT2:I0->O            1   0.468   0.920  img0/RED1 (RED_OBUF)
     OBUF:I->O                 4.602          RED_OBUF (RED)
    ----------------------------------------
    Total                     37.970ns (10.220ns logic, 27.750ns route)
                                       (26.9% logic, 73.1% route)

=========================================================================
CPU : 78.14 / 78.55 s | Elapsed : 78.00 / 78.00 s
 
--> 

Total memory usage is 120072 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   92 (   0 filtered)
Number of infos    :    1 (   0 filtered)