main.syr

这个是国外大学的项目代码

Synthesizing Unit <clkgen>.
    Related source file is "E:/work/digilentinc/XipHard/clkgen.vhd".
WARNING:Xst:646 - Signal <clkin> is assigned but never used.
WARNING:Xst:1780 - Signal <iCLK> is never used or assigned.
    Found 1-bit register for signal <iCLK2>.
    Found 1-bit register for signal <iCLK4>.
    Found 1-bit register for signal <iCLK8>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <clkgen> synthesized.


Synthesizing Unit <vga>.
    Related source file is "E:/work/digilentinc/XipHard/vga.vhd".
    Found 11-bit subtractor for signal <$n0004> created at line 66.
    Found 11-bit comparator equal for signal <$n0011> created at line 98.
    Found 11-bit comparator greatequal for signal <$n0012> created at line 59.
    Found 11-bit comparator less for signal <$n0013> created at line 59.
    Found 10-bit comparator greatequal for signal <$n0014> created at line 60.
    Found 10-bit comparator less for signal <$n0015> created at line 60.
    Found 11-bit comparator less for signal <$n0016> created at line 61.
    Found 10-bit comparator less for signal <$n0017> created at line 61.
    Found 11-bit adder for signal <hcount0>.
    Found 11-bit up counter for signal <ihc>.
    Found 28-bit up counter for signal <initvga>.
    Found 10-bit up counter for signal <ivc>.
    Summary:
	inferred   3 Counter(s).
	inferred   2 Adder/Subtractor(s).
	inferred   7 Comparator(s).
Unit <vga> synthesized.


Synthesizing Unit <prc2>.
    Related source file is "E:/work/digilentinc/XipHard/prc2.vhd".
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 11                                             |
    | Transitions        | 24                                             |
    | Inputs             | 11                                             |
    | Outputs            | 11                                             |
    | Clock              | CLK (rising_edge)                              |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 3-bit subtractor for signal <$n0000> created at line 134.
    Found 20-bit adder for signal <$n0036>.
    Found 20-bit adder for signal <$n0037>.
    Found 11-bit adder for signal <$n0043> created at line 238.
    Found 11-bit comparator equal for signal <$n0045> created at line 237.
    Found 11-bit comparator equal for signal <$n0047> created at line 238.
    Found 11-bit comparator equal for signal <$n0048> created at line 213.
    Found 2-bit up counter for signal <CCOLOR>.
    Found 20-bit register for signal <CDESTADR>.
    Found 11-bit up counter for signal <CHEIGHT>.
    Found 20-bit register for signal <CSRCADR>.
    Found 11-bit up counter for signal <CWIDTH>.
    Found 1-bit register for signal <iBUSY>.
    Found 3-bit register for signal <iPRCNR>.
    Found 1-bit register for signal <iPRCSTART>.
    Found 1-bit register for signal <iPROCESS>.
    Found 1-bit register for signal <iRDBUFF>.
    Found 1-bit register for signal <iRDDATA>.
    Found 1-bit register for signal <iRDDEST>.
    Found 1-bit register for signal <iRDEND>.
    Found 1-bit register for signal <iRDPRC>.
    Found 1-bit register for signal <iRDSRC>.
    Found 1-bit register for signal <iRDSTART>.
    Found 1-bit register for signal <iWRDATA>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   3 Counter(s).
	inferred  54 D-type flip-flop(s).
	inferred   4 Adder/Subtractor(s).
	inferred   3 Comparator(s).
Unit <prc2> synthesized.


Synthesizing Unit <imgctrl>.
    Related source file is "E:/work/digilentinc/XipHard/imgctrl.vhd".
    Found 20-bit register for signal <SADR>.
    Found 11-bit register for signal <IMGH>.
    Found 11-bit register for signal <IMGW>.
    Found 4-bit comparator not equal for signal <$n0010> created at line 46.
    Found 4-bit up counter for signal <ctrlst>.
    Found 4-bit register for signal <iIMGNR>.
    Summary:
	inferred   1 Counter(s).
	inferred  46 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <imgctrl> synthesized.


Synthesizing Unit <ctrl>.
    Related source file is "E:/work/digilentinc/XipHard/ctrl.vhd".
WARNING:Xst:647 - Input <CDI<7:4>> is never used.
    Found 5-bit comparator not equal for signal <$n0013> created at line 134.
    Found 4-bit comparator greater for signal <$n0015> created at line 118.
    Found 4-bit comparator less for signal <$n0016> created at line 123.
    Found 4-bit comparator greater for signal <$n0017> created at line 121.
    Found 3-bit comparator greater for signal <$n0019> created at line 109.
    Found 3-bit comparator less for signal <$n0020> created at line 114.
    Found 3-bit comparator greater for signal <$n0021> created at line 112.
    Found 5-bit register for signal <clockBTN>.
    Found 3-bit up counter for signal <ctrlst>.
    Found 4-bit updown counter for signal <iIMGNR>.
    Found 1-bit register for signal <iPRCDO>.
    Found 3-bit updown counter for signal <iPRCNR>.
    Found 4-bit register for signal <maximgnr>.
    Found 3-bit register for signal <maxprcnr>.
    Found 5-bit register for signal <prevBTN>.
    Summary:
	inferred   3 Counter(s).
	inferred  18 D-type flip-flop(s).
	inferred   7 Comparator(s).
Unit <ctrl> synthesized.


Synthesizing Unit <sram>.
    Related source file is "E:/work/digilentinc/XipHard/sram.vhd".
    Found 1-bit register for signal <RAMOE>.
    Found 1-bit register for signal <RAMCS0>.
    Found 1-bit register for signal <RAMCS1>.
    Found 1-bit register for signal <RAMWR>.
    Found 19-bit register for signal <RAMADR>.
    Found 8-bit tristate buffer for signal <RAMDB>.
    Found 8-bit register for signal <SDO>.
    Found 8-bit 4-to-1 multiplexer for signal <$n0023>.
    Found 8-bit register for signal <Mtridata_RAMDB> created at line 75.
    Found 1-bit register for signal <Mtrien_RAMDB> created at line 75.
    Summary:
	inferred  40 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
	inferred   8 Tristate(s).
Unit <sram> synthesized.


Synthesizing Unit <img>.
    Related source file is "E:/work/digilentinc/XipHard/img.vhd".
WARNING:Xst:647 - Input <SWT<4:0>> is never used.
WARNING:Xst:1780 - Signal <hinc> is never used or assigned.
Unit <img> synthesized.


Synthesizing Unit <seg7>.
    Related source file is "E:/work/digilentinc/XipHard/seg7.vhd".
    Found 16x7-bit ROM for signal <SEG>.
    Found 1-of-4 decoder for signal <AN>.
    Found 19-bit up counter for signal <cnt>.
    Found 4-bit 4-to-1 multiplexer for signal <HEX>.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Counter(s).
	inferred   4 Multiplexer(s).
	inferred   1 Decoder(s).
Unit <seg7> synthesized.


Synthesizing Unit <epp>.
    Related source file is "E:/work/digilentinc/XipHard/epp.vhd".
    Found 8-bit tristate buffer for signal <EPPDB>.
    Found 20-bit register for signal <ADR>.
    Found 20-bit up counter for signal <CNTADR>.
    Found 1-bit register for signal <CNTRAM>.
    Found 1-bit register for signal <CNTRAM2>.
    Found 2-bit up counter for signal <CNTSTATE>.
    Found 8-bit register for signal <idADR>.
    Found 2-bit register for signal <iDSPMODE>.
    Found 3-bit register for signal <iHDELAY>.
    Found 1-bit register for signal <iIMGCH>.
    Found 4-bit register for signal <iIMGNR>.
    Found 1-bit register for signal <iPRCCH>.
    Found 3-bit register for signal <iPRCNR>.
    Found 3-bit register for signal <iPWMNR>.
    Found 4-bit register for signal <iVDELAY>.
    Found 8-bit register for signal <ramDATA>.
    Found 8-bit register for signal <ramDATA2>.
    Found 1-bit register for signal <sRAMOP>.
    Summary:
	inferred   2 Counter(s).
	inferred  68 D-type flip-flop(s).
	inferred   8 Tristate(s).
Unit <epp> synthesized.


Synthesizing Unit <main>.
    Related source file is "E:/work/digilentinc/XipHard/main.vhd".
Unit <main> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <state[1:11]> with one-hot encoding.
----------------------------
 State       | Encoding
----------------------------
 idle        | 00000000001
 rdprc       | 00000000010
 rdsrc       | 00000000100
 rddest      | 00000001000
 prcstart    | 00000010000
 rdstart     | 00000100000
 rddata      | 00001000000
 rdend       | 00010000000
 wrdatastart | 00100000000
 wrdata      | 01000000000
 wrdataend   | 10000000000
----------------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 4
 16x7-bit ROM                      : 1
 32x4-bit ROM                      : 3
# Adders/Subtractors               : 23
 11-bit adder                      : 2
 11-bit subtractor                 : 1
 16-bit adder                      : 17
 20-bit adder                      : 2
 3-bit subtractor                  : 1
# Counters                         : 26
 10-bit up counter                 : 1
 11-bit up counter                 : 7
 19-bit up counter                 : 1
 2-bit up counter                  : 2
 20-bit up counter                 : 4
 28-bit up counter                 : 1
 3-bit up counter                  : 1
 3-bit updown counter              : 1
 4-bit up counter                  : 4
 4-bit updown counter              : 1
 9-bit up counter                  : 2
 9-bit updown counter              : 1
# Registers                        : 283
 1-bit register                    : 194
 11-bit register                   : 2
 16-bit register                   : 30
 19-bit register                   : 1
 2-bit register                    : 3
 20-bit register                   : 5
 3-bit register                    : 5
 4-bit register                    : 6
 5-bit register                    : 2
 8-bit register                    : 35
# Shift Registers                  : 3
 12-bit shift register             : 1
 6-bit shift register              : 1
 8-bit shift register              : 1
# Comparators                      : 28
 10-bit comparator greatequal      : 1
 10-bit comparator less            : 4
 11-bit comparator equal           : 4
 11-bit comparator greatequal      : 1
 11-bit comparator less            : 6
 11-bit comparator not equal       : 2
 3-bit comparator greater          : 2
 3-bit comparator less             : 1
 4-bit comparator greater          : 2
 4-bit comparator less             : 1
 4-bit comparator not equal        : 1
 5-bit comparator not equal        : 1
 9-bit comparator less             : 2
# Multiplexers                     : 40
 1-bit 16-to-1 multiplexer         : 6