main.syr

这个是国外大学的项目代码

Synthesizing Unit <cround>.
    Related source file is "E:/work/digilentinc/XipHard/cround.vhd".
    Found 8-bit register for signal <iDO>.
    Found 8-bit 4-to-1 multiplexer for signal <res>.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
Unit <cround> synthesized.


Synthesizing Unit <cdiv>.
    Related source file is "E:/work/digilentinc/XipHard/cdiv.vhd".
WARNING:Xst:647 - Input <MASK<3>> is never used.
    Found 16-bit register for signal <iDO>.
    Summary:
	inferred  16 D-type flip-flop(s).
Unit <cdiv> synthesized.


Synthesizing Unit <cnop>.
    Related source file is "E:/work/digilentinc/XipHard/cnop.vhd".
    Found 16-bit register for signal <iDO>.
    Summary:
	inferred  16 D-type flip-flop(s).
Unit <cnop> synthesized.


Synthesizing Unit <cadd>.
    Related source file is "E:/work/digilentinc/XipHard/cadd.vhd".
    Found 16-bit register for signal <iDO>.
    Found 16-bit adder for signal <res>.
    Summary:
	inferred  16 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <cadd> synthesized.


Synthesizing Unit <c2comp>.
    Related source file is "E:/work/digilentinc/XipHard/c2comp.vhd".
    Found 16-bit adder for signal <$n0000> created at line 40.
    Found 16-bit register for signal <iDO>.
    Summary:
	inferred  16 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <c2comp> synthesized.


Synthesizing Unit <cmul>.
    Related source file is "E:/work/digilentinc/XipHard/cmul.vhd".
WARNING:Xst:647 - Input <MASK<3>> is never used.
    Found 16-bit register for signal <iDO>.
    Summary:
	inferred  16 D-type flip-flop(s).
Unit <cmul> synthesized.


Synthesizing Unit <cbuff>.
    Related source file is "E:/work/digilentinc/XipHard/cbuff.vhd".
    Found 8-bit 4-to-1 multiplexer for signal <DO>.
    Found 11-bit comparator not equal for signal <$n0011> created at line 45.
    Found 11-bit register for signal <iWIDTH>.
    Found 11-bit up counter for signal <rdaddr>.
    Found 2-bit register for signal <rdaddrcs0>.
    Found 11-bit up counter for signal <wraddr>.
    Summary:
	inferred   2 Counter(s).
	inferred  13 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   8 Multiplexer(s).
Unit <cbuff> synthesized.


Synthesizing Unit <creg>.
    Related source file is "E:/work/digilentinc/XipHard/creg.vhd".
    Found 8-bit register for signal <iDO>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <creg> synthesized.


Synthesizing Unit <clog>.
    Related source file is "E:/work/digilentinc/XipHard/clog.vhd".
Unit <clog> synthesized.


Synthesizing Unit <cfifo>.
    Related source file is "E:/work/digilentinc/XipHard/cfifo.vhd".
    Found 9-bit up counter for signal <rdaddr>.
    Found 9-bit updown counter for signal <size>.
    Found 9-bit up counter for signal <wraddr>.
    Summary:
	inferred   3 Counter(s).
Unit <cfifo> synthesized.


Synthesizing Unit <conv>.
    Related source file is "E:/work/digilentinc/XipHard/conv.vhd".
    Found 12-bit shift register for signal <valid<11>>.
    Summary:
	inferred   1 Shift register(s).
Unit <conv> synthesized.


Synthesizing Unit <imgctrl2>.
    Related source file is "E:/work/digilentinc/XipHard/imgctrl2.vhd".
    Found 4-bit up counter for signal <iADR>.
    Found 20-bit register for signal <iIMGADR>.
    Found 11-bit register for signal <iIMGH>.
    Found 11-bit register for signal <iIMGW>.
    Summary:
	inferred   1 Counter(s).
	inferred  42 D-type flip-flop(s).
Unit <imgctrl2> synthesized.


Synthesizing Unit <prcctrl>.
    Related source file is "E:/work/digilentinc/XipHard/prcctrl.vhd".
    Found 4-bit up counter for signal <iADR>.
    Found 4-bit register for signal <iIMGDEST>.
    Found 4-bit register for signal <iIMGSRC>.
    Found 8-bit register for signal <iMASK0>.
    Found 8-bit register for signal <iMASK1>.
    Found 8-bit register for signal <iMASK2>.
    Found 8-bit register for signal <iMASK3>.
    Found 8-bit register for signal <iMASK4>.
    Found 8-bit register for signal <iMASK5>.
    Found 8-bit register for signal <iMASK6>.
    Found 8-bit register for signal <iMASK7>.
    Found 8-bit register for signal <iMASK8>.
    Found 8-bit register for signal <iMASK9>.
    Summary:
	inferred   1 Counter(s).
	inferred  88 D-type flip-flop(s).
Unit <prcctrl> synthesized.


Synthesizing Unit <pwm2xeq>.
    Related source file is "E:/work/digilentinc/XipHard/pwm2xeq.vhd".
WARNING:Xst:647 - Input <DI<3:0>> is never used.
    Found 1-bit 16-to-1 multiplexer for signal <DO>.
    Summary:
	inferred   1 Multiplexer(s).
Unit <pwm2xeq> synthesized.


Synthesizing Unit <pwminv2x>.
    Related source file is "E:/work/digilentinc/XipHard/pwminv2x.vhd".
WARNING:Xst:647 - Input <DI<2:0>> is never used.
    Found 1-bit 32-to-1 multiplexer for signal <DO>.
    Summary:
	inferred   1 Multiplexer(s).
Unit <pwminv2x> synthesized.


Synthesizing Unit <pwm2x>.
    Related source file is "E:/work/digilentinc/XipHard/pwm2x.vhd".
WARNING:Xst:647 - Input <DI<2:0>> is never used.
    Found 1-bit 32-to-1 multiplexer for signal <DO>.
    Summary:
	inferred   1 Multiplexer(s).
Unit <pwm2x> synthesized.


Synthesizing Unit <pwm18>.
    Related source file is "E:/work/digilentinc/XipHard/pwm18.vhd".
WARNING:Xst:647 - Input <DI<1:0>> is never used.
    Found 32x4-bit ROM for signal <pwmsel3>.
    Found 1-bit 32-to-1 multiplexer for signal <DO>.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Multiplexer(s).
Unit <pwm18> synthesized.


Synthesizing Unit <pwmlo>.
    Related source file is "E:/work/digilentinc/XipHard/pwmlo.vhd".
WARNING:Xst:647 - Input <DI<2:0>> is never used.
    Found 1-bit 32-to-1 multiplexer for signal <DO>.
    Summary:
	inferred   1 Multiplexer(s).
Unit <pwmlo> synthesized.


Synthesizing Unit <pwmhi>.
    Related source file is "E:/work/digilentinc/XipHard/pwmhi.vhd".
WARNING:Xst:647 - Input <DI<2:0>> is never used.
Unit <pwmhi> synthesized.


Synthesizing Unit <pwmeq>.
    Related source file is "E:/work/digilentinc/XipHard/pwmeq.vhd".
WARNING:Xst:647 - Input <DI<3:0>> is never used.
    Found 1-bit 16-to-1 multiplexer for signal <DO>.
    Summary:
	inferred   1 Multiplexer(s).
Unit <pwmeq> synthesized.


Synthesizing Unit <pwmmd>.
    Related source file is "E:/work/digilentinc/XipHard/pwmmd.vhd".
WARNING:Xst:647 - Input <DI<2:0>> is never used.
Unit <pwmmd> synthesized.


Synthesizing Unit <imgrgb16>.
    Related source file is "E:/work/digilentinc/XipHard/imgrgb16.vhd".
    Found 8-bit register for signal <DBLU>.
    Found 8-bit register for signal <DGRN>.
    Found 8-bit register for signal <DRED>.
    Found 20-bit register for signal <IADR>.
    Found 8-bit 8-to-1 multiplexer for signal <$n0001> created at line 62.
    Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0003>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0009>.
    Found 8-bit 8-to-1 multiplexer for signal <$n0013> created at line 62.
    Found 8-bit 8-to-1 multiplexer for signal <$n0015> created at line 62.
    Found 10-bit comparator less for signal <$n0035> created at line 45.
    Found 11-bit comparator less for signal <$n0036> created at line 45.
    Found 10-bit comparator less for signal <$n0037> created at line 43.
    Found 11-bit comparator less for signal <$n0038> created at line 43.
    Found 16-bit register for signal <epixel>.
    Found 6-bit shift register for signal <hinc<0>>.
    Found 20-bit up counter for signal <oadr>.
    Found 16-bit register for signal <opixel>.
    Summary:
	inferred   1 Counter(s).
	inferred  76 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred  32 Multiplexer(s).
	inferred   1 Shift register(s).
Unit <imgrgb16> synthesized.


Synthesizing Unit <imgrgb24>.
    Related source file is "E:/work/digilentinc/XipHard/imgrgb24.vhd".
    Found 8-bit register for signal <DBLU>.
    Found 8-bit register for signal <DGRN>.
    Found 8-bit register for signal <DRED>.
    Found 20-bit register for signal <IADR>.
    Found 8-bit 4-to-1 multiplexer for signal <$n0007>.
    Found 8-bit 4-to-1 multiplexer for signal <$n0011>.
    Found 8-bit 4-to-1 multiplexer for signal <$n0012>.
    Found 9-bit comparator less for signal <$n0023> created at line 44.
    Found 11-bit comparator less for signal <$n0024> created at line 44.
    Found 9-bit comparator less for signal <$n0025> created at line 42.
    Found 11-bit comparator less for signal <$n0026> created at line 42.
    Found 20-bit up counter for signal <eadr>.
    Found 8-bit register for signal <eblu>.
    Found 8-bit register for signal <egrn>.
    Found 8-bit register for signal <ered>.
    Found 8-bit shift register for signal <hinc<0>>.
    Found 20-bit up counter for signal <oadr>.
    Found 8-bit register for signal <oblu>.
    Found 8-bit register for signal <ogrn>.
    Found 8-bit register for signal <ored>.
    Summary:
	inferred   2 Counter(s).
	inferred  92 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred  24 Multiplexer(s).
	inferred   1 Shift register(s).
Unit <imgrgb24> synthesized.


Synthesizing Unit <pixel>.
    Related source file is "E:/work/digilentinc/XipHard/pixel.vhd".
    Found 1-bit 8-to-1 multiplexer for signal <GRN>.
    Found 1-bit 8-to-1 multiplexer for signal <RED>.
    Found 1-bit 8-to-1 multiplexer for signal <BLU>.
    Summary:
	inferred   3 Multiplexer(s).
Unit <pixel> synthesized.